From 06779c5442c1ceb171a1320b6c53a8a26c6d6480 Mon Sep 17 00:00:00 2001 From: Daniele Verducci su MatissePenguin Date: Wed, 6 Jan 2021 00:19:15 +0100 Subject: [PATCH] Loses sync when loading from memory --- .../software/avr-assembly/main.asm | 116 ++++++++++++------ 1 file changed, 79 insertions(+), 37 deletions(-) diff --git a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm index bb0b361..2a4427e 100644 --- a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm +++ b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm @@ -4,9 +4,12 @@ .include "atmega1284definition.asm" ; define constant -.equ SYNC_PIN = PD7 ; Sync pin is on Port D 7 (pin 21) -.equ VIDEO_PIN = PD6 ; Video pin is on Port D 6 (pin 20) -.equ DEBUG_PIN = PD5 ; Video pin is on Port D 5 (pin 19) +.equ SYNC_PIN = PC0 ; Sync pin (pin 22) +.equ VIDEO_PIN = PD7 ; Video pin (pin 21) +.equ DEBUG_PIN = PC1 ; DEBUG: Single vertical sync pulse to trigger oscilloscope (pin 23) + +; memory +.equ FRAMEBUFFER = 0x100 ; start vector .org 0x0000 @@ -14,11 +17,39 @@ ; main program main: - sbi DDRD, SYNC_PIN ; set pin as output - sbi DDRD, VIDEO_PIN ; set pin as output - sbi DDRD, DEBUG_PIN ; set pin as output + sbi DDRC, SYNC_PIN ; set pin as output + sbi DDRC, DEBUG_PIN ; set pin as output + ldi r16, 0xFF + out DDRD, r16 ; set port as output + + + ; Load ram addr into register X + ldi r16,0x00 + mov r0,r16 + ldi r16,0x01 + mov r1,r16 + mov XL,r0 + mov XH,r1 + + ; DEBUG: loads some static data in ram + ldi r18, 255 + fill_mem_loop1: + st X+, r18 + dec r18 + brne fill_mem_loop1 + ; END DEBUG v_refresh_loop: + ; reset memory position counter + ;ldi XL, 0x00 + ;ldi XH, 0x01 + ldi r16,0x00 + mov r0,r16 + ldi r16,0x01 + mov r1,r16 + mov XL,r0 + mov XH,r1 + ; start 5 long sync pulses call long_sync call long_sync @@ -41,31 +72,42 @@ v_refresh_loop: ldi r17, 152 ; line counter h_picture_loop: call line_sync - ; start image: 52uS, 1247 cycles @ 24Mhz - ; 3 bande da 416 cicli + ; start line pixels: 52uS, 1247 cycles @ 24Mhz + ldi r18, 52 ; 1 cycle + l_sync_video_loop: ; 24 cycles + ; Load a byte from memory into PORTD register and increment the counter. + ; This also displays byte's MSB pixel "for free", as the video pin is PD7 + ; (last bit of PORTD). + ;ld r19, X+ ; 2 cycles + + ld r19, X ; 1 cycle + nop - ldi r18, 59 ; 1 cycle - l_sync_video_loop1: - sbi PORTD, VIDEO_PIN ; video goes high ; 2 cycle - dec r18 ; 1 cycle - cbi PORTD, VIDEO_PIN ; video goes low ; 2 cycle - brne l_sync_video_loop1 ; 2 cycle if true, 1 if false - - ldi r18, 137 ; 1 cycle - l_sync_video_loop2: - dec r18 ; 1 cycle - brne l_sync_video_loop2 ; 2 cycle if true, 1 if false - - sbi PORTD, VIDEO_PIN ; video goes high - - ldi r18, 138 ; 1 cycle - l_sync_video_loop3: - dec r18 ; 1 cycle - brne l_sync_video_loop3 ; 2 cycle if true, 1 if false - cbi PORTD, VIDEO_PIN ; video goes low - - ; end image + out PORTD, r19 ; 1 cycle + ; Shift the byte to the left to show another bit (do it 7 times) + lsl r19 ; 1 cycle + out PORTD, r19 + nop + lsl r19 ; 1 cycle + out PORTD, r19 + nop + lsl r19 ; 1 cycle + out PORTD, r19 + nop + lsl r19 ; 1 cycle + out PORTD, r19 + nop + lsl r19 ; 1 cycle + out PORTD, r19 + nop + lsl r19 ; 1 cycle + out PORTD, r19 + nop ; 1 cycle + dec r18 ; 1 cycle + brne l_sync_video_loop ; 2 cycles if jumps (1 if continues) + ; end line pixels + cbi PORTD, VIDEO_PIN ; video pin goes low before sync dec r17 ; decrement line counter brne h_picture_loop ; if not 0, repeat h_picture_loop @@ -83,8 +125,8 @@ v_refresh_loop: ; end 6 short sync pulses ; debug - sbi PORTD, DEBUG_PIN ; high - cbi PORTD, DEBUG_PIN ; low + sbi PORTC, DEBUG_PIN ; high + cbi PORTC, DEBUG_PIN ; low ; debug jmp v_refresh_loop @@ -92,7 +134,7 @@ v_refresh_loop: long_sync: ; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz) - cbi PORTD, SYNC_PIN ; sync goes low (0v) ; 2 cycle + cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle ldi r18, 120 ; 1 cycle long_sync_low_loop: ; requires 6 cpu cycles @@ -102,7 +144,7 @@ long_sync: dec r18 ; 1 cycle brne long_sync_low_loop ; 2 cycle if true, 1 if false - sbi PORTD, SYNC_PIN ; sync goes high (0.3v) + sbi PORTC, SYNC_PIN ; sync goes high (0.3v) ldi r18, 15 ; 1 cycle long_sync_high_loop: ; requires 3 cpu cycles @@ -113,14 +155,14 @@ long_sync: short_sync: ; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz) - cbi PORTD, SYNC_PIN ; sync goes low (0v) ; 2 cycle + cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle ldi r18, 15 ; 1 cycle short_sync_low_loop: ; requires 3 cpu cycles dec r18 ; 1 cycle brne short_sync_low_loop ; 2 cycle if true, 1 if false - sbi PORTD, SYNC_PIN ; sync goes high (0.3v) + sbi PORTC, SYNC_PIN ; sync goes high (0.3v) ldi r18, 120 ; 1 cycle short_sync_high_loop: ; requires 6 cpu cycles @@ -135,12 +177,12 @@ short_sync: line_sync: ; line sync & front porch ; start line sync: 4uS, 96 cycles @ 24Mhz - cbi PORTD, SYNC_PIN ; sync goes low (0v) ; 2 cycle + cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle ldi r18, 32 ; 1 cycle l_sync_pulse_loop: ; requires 3 cpu cycles dec r18 ; 1 cycle brne l_sync_pulse_loop ; 2 cycle if true, 1 if false - sbi PORTD, SYNC_PIN ; sync goes high (0.3v) + sbi PORTC, SYNC_PIN ; sync goes high (0.3v) ; end line sync ; start back porch: 8uS, 192 cycles @ 24Mhz