From 17fdf97f752677a1ec900bf79ba87854d995762c Mon Sep 17 00:00:00 2001
From: Daniele Verducci su MatissePenguin <daniele.verducci@gmail.com>
Date: Tue, 19 Jan 2021 20:55:11 +0100
Subject: [PATCH] Copying data bus to framebuffer memory, but ignoring clock
 signal

---
 .../software/avr-assembly/communication.asm   | 22 +++++++++++++++++++
 .../software/avr-assembly/main.asm            | 20 +++++++++++++----
 2 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/communication.asm b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/communication.asm
index 34af32e..b8d1b82 100644
--- a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/communication.asm
+++ b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/communication.asm
@@ -5,3 +5,25 @@
 
 ; This module manages the communication between Pat80 and
 ; the video adapter.
+; The data port is PORTB. The CLK (clock) signal is on PORTD0
+; and the RS (register select) on PORTD1
+
+; Initializes and waits for a byte on PORTB
+comm_init:
+    ; Set Z to framebuffer start
+	ldi r31, high(FRAMEBUFFER<<1)
+	ldi r30, low(FRAMEBUFFER<<1)
+    comm_wait_byte:
+        in r24, PINB   ; read PORTB
+        ; Check continuously CLK until a LOW is found
+        sbic PORTD, CLK_PIN
+        jmp comm_wait_byte
+        ; CLK triggered: Copy PORTB to the next framebuffer byte
+        st Z+, r24
+        ; if reached the last framebuffer byte, exit cycle
+		cpi r31, 0b00111110
+		brne comm_wait_byte	; if not 0, repeat h_picture_loop
+		cpi r30, 0b11000000
+		brne comm_wait_byte	; if not 0, repeat h_picture_loop
+        jmp comm_init ; filled all memory: reset framebuffer position
+
diff --git a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm
index 41f9559..45f9588 100644
--- a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm
+++ b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm
@@ -19,9 +19,6 @@
 ;
 
 .include "m1284def.inc" ; Atmega 1280 device definition
-.include "video_generator.asm" ; Asyncronous timer-interrupt-based video generation
-.include "character_generator.asm" ; Character generator
-.include "communication.asm" ; Communication with Pat80
 
 ; reserved registers
 .def A = r0	; accumulator
@@ -30,6 +27,7 @@
 ; define constant
 .equ SYNC_PIN = PC0			; Sync pin (pin 22)
 .equ DEBUG_PIN = PC1		; DEBUG: Single vertical sync pulse to trigger oscilloscope (pin 23)
+.equ CLK_PIN = PD7
 
 ; memory
 .equ FRAMEBUFFER = 0x100
@@ -46,8 +44,13 @@ main:
 	; pins setup
 	sbi	DDRC, SYNC_PIN		; set pin as output
 	sbi	DDRC, DEBUG_PIN		; set pin as output
+	cbi DDRD, CLK_PIN		; set pin as input
 	ldi	r16, 0xFF
 	out DDRA, r16			; set port as output (contains video pin)
+	ldi	r16, 0x00
+	out DDRB, r16			; set port as input (used as data bus)
+	
+
 
 	; *** timer setup (use 16-bit counter TC1) ***
 	; The Power Reduction TC1 and TC3 bits in the Power Reduction Registers (PRR0.PRTIM1 and
@@ -64,6 +67,15 @@ main:
     SEI
 	; Timer setup completed.
 
-	; loop forever
+	; Wait for data (it never exits)
+	jmp comm_init
+
 	forever:
 		jmp forever
+
+
+
+
+.include "video_generator.asm" ; Asyncronous timer-interrupt-based video generation
+.include "character_generator.asm" ; Character generator
+.include "communication.asm" ; Communication with Pat80