From 1d4c4f8d3f62061a8332206d90732f4256902410 Mon Sep 17 00:00:00 2001 From: Daniele Verducci su MatissePenguin Date: Thu, 25 Feb 2021 23:26:13 +0100 Subject: [PATCH] Bugfix, refactoring --- .../avr-assembly/character_generator.asm | 26 +- .../avr-assembly/example_data/cat.asm | 12 +- .../software/avr-assembly/main.asm | 56 +- .../software/avr-assembly/video_generator.asm | 1540 ++++++++--------- 4 files changed, 817 insertions(+), 817 deletions(-) diff --git a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/character_generator.asm b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/character_generator.asm index 6677960..084946f 100644 --- a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/character_generator.asm +++ b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/character_generator.asm @@ -9,9 +9,15 @@ .equ LINE_COLUMNS = 46 ; number of columns (characters or chunks) per line ; Draws character in register A to the screen at current coords (Y) -; @param r16 (HIGH_ACCUM) ascii code to display -; @modifies r0 (A), r1, r2, r3, r16 (HIGH_ACCUM), r17, Y, Z +; @param (HIGH_ACCUM) ascii code to display +; @modifies r0 (A), r1, r2, r3, r17, HIGH_ACCUM, Y, Z draw_char: + ; Check char is valid + cpi HIGH_ACCUM, 0x7f + brlo draw_char_valid + ret + + draw_char_valid: ; Glyph's first byte is at: ; glyph_pointer = font_starting_mem_pos + (ascii_code * number_of_bytes_per_font) ; But all the fonts are 1 byte large, so a glyph is 1*height bytes: @@ -130,7 +136,7 @@ update_mem_pointer: ; ...+POS_COLUMN add r0, POS_COLUMN clr HIGH_ACCUM - adc r0, HIGH_ACCUM + adc r1, HIGH_ACCUM ; Set pointer to start of framebuffer ldi YL, low(FRAMEBUFFER) ldi YH, high(FRAMEBUFFER) @@ -138,3 +144,17 @@ update_mem_pointer: add YL, r0 adc YH, r1 ret + +clear_screen: + ldi YH, high(FRAMEBUFFER) + ldi YL, low(FRAMEBUFFER) + load_mem_loop: + clr HIGH_ACCUM + ;ser HIGH_ACCUM + st Y+, HIGH_ACCUM + ; if reached the last framebuffer byte, exit cycle + cpi YH, high(FRAMEBUFFER_END) + brne load_mem_loop ; if not 0, repeat h_picture_loop + cpi YL, low(FRAMEBUFFER_END) + brne load_mem_loop ; if not 0, repeat h_picture_loop + ret \ No newline at end of file diff --git a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/example_data/cat.asm b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/example_data/cat.asm index 633af47..1fa5b11 100644 --- a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/example_data/cat.asm +++ b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/example_data/cat.asm @@ -6,13 +6,13 @@ draw_cat: ldi ZH, high(CAT_IMAGE) ldi ZL, low(CAT_IMAGE) load_cat_loop: - lpm r17, Z+ - st Y+, r17 + lpm HIGH_ACCUM, Z+ + st Y+, HIGH_ACCUM ; wait - ser r19 - cat_wait_loop_1: - dec r19 - brne cat_wait_loop_1 + ; ser r19 + ; cat_wait_loop_1: + ; dec r19 + ; brne cat_wait_loop_1 ; if reached the last framebuffer byte, exit cycle cpi YH, high(FRAMEBUFFER_END) brne load_cat_loop ; if not 0, repeat h_picture_loop diff --git a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm index f1e3258..2cdb80a 100644 --- a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm +++ b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm @@ -25,32 +25,30 @@ .include "m1284def.inc" ; Atmega 1280 device definition ; *** reserved registers *** -; Cursor Position -; POS_COLUMN (0-46) represents the character/chunk column -; POS_ROWP (0-255) represent the chunk row. The caracter row is POS_ROWP/FONT_HEIGHT -.def POS_COLUMN = r21 -.def POS_ROWP = r20 -; Internal registers -.def A = r0 ; accumulator +; Video generator registers: +; X(R27, R26) .def STATUS = r25 ; signal status (see STATUS TABLE) -;POS_COARSE = Y ; coarse position (aligned to character column) -;DRAWING_BYTE = X ; current position in framebuffer +.def VG_HIGH_ACCUM = r24 ; an accumulator in high registers to be used only by video_generator in interrupt .def LINE_COUNTER = r23 -.def VG_HIGH_ACCUM = r22 ; an accumulator in high registers to be used only by video_generator in interrupt -.def HIGH_ACCUM = r16 ; an accumulator in high registers to be used outside of interrupts -; define constant +; Character generator registers: +.def POS_COLUMN = r22 ; POS_COLUMN (0-46) represents the character/chunk column +.def POS_ROWP = r21 ; POS_ROWP (0-255) represent the chunk row. The caracter row is POS_ROWP/FONT_HEIGHT +.def HIGH_ACCUM = r20 ; an accumulator in high registers to be used outside of interrupts +.def A = r0 ; general purpose accumulator to be used outside of interrupts + +; Hardware pins and ports .equ VIDEO_PORT_OUT = PORTA ; Used all PORTA, but connected only PA0 .equ SYNC_PIN = PC0 ; Sync pin (pin 22) .equ DEBUG_PIN = PC1 ; DEBUG: Single vertical sync pulse to trigger oscilloscope (pin 23) -.equ DATA_PORT_IN = PINB -.equ CLK_PIN = PD0 -.equ RS_PIN = PD1 -.equ BUSY_PIN = PD2 +.equ DATA_PORT_IN = PIND +.equ CLK_PIN = PC2 +.equ RS_PIN = PC3 +.equ BUSY_PIN = PC4 -; memory -.equ FRAMEBUFFER = 0x0100 -.equ FRAMEBUFFER_END = 0x2F00 +; Memory map +.equ FRAMEBUFFER = 0x0F70 +.equ FRAMEBUFFER_END = 0x3C00 .equ SCREEN_HEIGHT = 248 ; start vector @@ -77,19 +75,7 @@ main: ; **** MEMORY SETUP **** - ; clear ram - ;*** Load data into ram *** - Set X to 0x0100 - ldi XH, high(FRAMEBUFFER) - ldi XL, low(FRAMEBUFFER) - load_mem_loop: - clr r17 - st X+, r17 - ; if reached the last framebuffer byte, exit cycle - cpi XH, 0b00111110 - brne load_mem_loop ; if not 0, repeat h_picture_loop - cpi XL, 0b11000000 - brne load_mem_loop ; if not 0, repeat h_picture_loop + call clear_screen @@ -118,7 +104,7 @@ main: ; **** MAIN ROUTINE **** ; Wait for data (it never exits) - ; jmp comm_init + ;jmp comm_init ; draw example image @@ -144,7 +130,7 @@ main: inc r18 cpi r18, 0x5B brne draw_chars - call draw_carriage_return + ; call draw_carriage_return jmp dctest @@ -160,4 +146,4 @@ main: .include "character_generator.asm" ; Character generator ;.include "communication.asm" ; Communication with Pat80 .include "font.asm" ; Font face -.include "example_data/cat.asm" ; Cat image +;.include "example_data/cat.asm" ; Cat image diff --git a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/video_generator.asm b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/video_generator.asm index 34eb029..ef0816f 100644 --- a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/video_generator.asm +++ b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/video_generator.asm @@ -3,6 +3,8 @@ ; * Video generator module * ; ******************************************* +; Uses registers X(R27, R26), STATUS (R25), VG_HIGH_ACCUM (r24), LINE_COUNTER (r23) + ; Implemented following timings in http://blog.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/ and http://www.kolumbus.fi/pami1/video/pal_ntsc.html ; Every line, for 46 times, it loads a byte from memory into PORTA register and then shifts the byte to the left to show another bit (do it 7 times) ; This also displays byte's MSB pixel "for free", as the video pin is PD7 (last bit of PORTA). @@ -16,10 +18,10 @@ ; The screen draw is divided in phases. Every phase does something. I.e. phases 0 to 9 ; represents the first 5 long syncs: ; (sync goes low, wait 30uS, sync goes high, wait 2uS) x 5 times = 10 phases -; When the interrupt is called, it uses register r25 (STATUS) to decide what to do. +; When the interrupt is called, it uses register STATUS to decide what to do. ; ; STATUS TABLE: -; R25 (STATUS): Current status (what the interrupt should do when fired): +; reg STATUS: Current status (what the interrupt should do when fired): ; 0-9 = long sync ; 10-19 = short sync ; 20-44 = draw empty lines (top vertical padding) @@ -72,10 +74,10 @@ long_sync: ; sync pin is high (sync is not occuring) cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle ; set timer in 30uS (reset timer counter) - ldi r27, high(TIMER_DELAY_30US) - ldi r26, low(TIMER_DELAY_30US) - sts TCNT1H,r27 - sts TCNT1L,r26 + ldi XH, high(TIMER_DELAY_30US) + ldi XL, low(TIMER_DELAY_30US) + sts TCNT1H,XH + sts TCNT1L,XL ; clear BUSY pin to indicate the mc is again responsive from now on cbi PORTD, BUSY_PIN reti @@ -84,10 +86,10 @@ long_sync: ; sync pin is low (sync is occuring) sbi PORTC, SYNC_PIN ; sync goes high (0.3v) ; set timer in 2uS: - ldi r27, high(TIMER_DELAY_2US) - ldi r26, low(TIMER_DELAY_2US) - sts TCNT1H,r27 - sts TCNT1L,r26 + ldi XH, high(TIMER_DELAY_2US) + ldi XL, low(TIMER_DELAY_2US) + sts TCNT1H,XH + sts TCNT1L,XL ; clear BUSY pin to indicate the mc is again responsive from now on cbi PORTD, BUSY_PIN reti @@ -101,10 +103,10 @@ short_sync: ; sync pin is high (sync is not occuring) cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle ; set timer in 2uS (reset timer counter) - ldi r27, high(TIMER_DELAY_2US) - ldi r26, low(TIMER_DELAY_2US) - sts TCNT1H,r27 - sts TCNT1L,r26 + ldi XH, high(TIMER_DELAY_2US) + ldi XL, low(TIMER_DELAY_2US) + sts TCNT1H,XH + sts TCNT1L,XL ; clear BUSY pin to indicate the mc is again responsive from now on cbi PORTD, BUSY_PIN reti @@ -113,10 +115,10 @@ short_sync: ; sync pin is low (sync is occuring) sbi PORTC, SYNC_PIN ; sync goes high (0.3v) ; set timer in 30uS: - ldi r27, high(TIMER_DELAY_30US) - ldi r26, low(TIMER_DELAY_30US) - sts TCNT1H,r27 - sts TCNT1L,r26 + ldi XH, high(TIMER_DELAY_30US) + ldi XL, low(TIMER_DELAY_30US) + sts TCNT1H,XH + sts TCNT1L,XL ; clear BUSY pin to indicate the mc is again responsive from now on cbi PORTD, BUSY_PIN reti @@ -128,10 +130,10 @@ empty_line: ; sync pin is high (sync is not occuring) cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle ; set timer in 2uS (reset timer counter) - ldi r27, high(TIMER_DELAY_4US) - ldi r26, low(TIMER_DELAY_4US) - sts TCNT1H,r27 - sts TCNT1L,r26 + ldi XH, high(TIMER_DELAY_4US) + ldi XL, low(TIMER_DELAY_4US) + sts TCNT1H,XH + sts TCNT1L,XL ; clear BUSY pin to indicate the mc is again responsive from now on cbi PORTD, BUSY_PIN reti @@ -140,19 +142,15 @@ empty_line: ; sync pin is low (sync is occuring) sbi PORTC, SYNC_PIN ; sync goes high (0.3v) ; set timer in 30uS: - ldi r27, high(TIMER_DELAY_60US) - ldi r26, low(TIMER_DELAY_60US) - sts TCNT1H,r27 - sts TCNT1L,r26 + ldi XH, high(TIMER_DELAY_60US) + ldi XL, low(TIMER_DELAY_60US) + sts TCNT1H,XH + sts TCNT1L,XL ; clear BUSY pin to indicate the mc is again responsive from now on cbi PORTD, BUSY_PIN reti draw_picture: - ; save X register - push XH - push XL - ; set X register to framebuffer start ldi XH, high(FRAMEBUFFER) ldi XL, low(FRAMEBUFFER) @@ -187,10 +185,6 @@ draw_picture: brne h_picture_loop ; if not 0, repeat h_picture_loop ; 2 cycle if true, 1 if false ; end picture lines - ; restore X register - pop XL - pop XH - ; video pin goes low before sync clr VG_HIGH_ACCUM ; 1 cycle out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle @@ -207,1158 +201,1158 @@ draw_line: ; 46 chunks of 8 pixels ; chunk 1 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 2 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 3 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 4 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 5 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 6 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 7 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 8 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 9 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 10 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 11 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 12 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 13 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 14 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 15 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 16 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 17 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 18 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 19 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 20 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 21 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 22 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 23 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 24 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 25 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 26 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 27 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 28 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 29 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 30 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 31 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 32 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 33 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 34 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 35 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 36 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 37 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 38 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 39 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 40 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 41 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 42 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 43 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 44 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 45 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ; chunk 46 - ld A, X+ ; load pixel ; 2 cycles - out VIDEO_PORT_OUT, A ; 1 cycle + ld VG_HIGH_ACCUM, X+ ; load pixel ; 2 cycles + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle nop ; 1 cycle - lsr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + lsr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle - ; blank right margin - clr A ; 1 cycle - out VIDEO_PORT_OUT, A ; 1 cycle + ; blank right margin (write 0 to video port and wait) + clr VG_HIGH_ACCUM ; 1 cycle + out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle ldi VG_HIGH_ACCUM, 28 ; 1 cycle eol_porch_loop: ; requires 3 cpu cycles dec VG_HIGH_ACCUM ; 1 cycle