diff --git a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/fuses.conf b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/fuses.conf
index 76a3a9a..fc9d0a0 100644
--- a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/fuses.conf
+++ b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/fuses.conf
@@ -1,4 +1,4 @@
-fuses_lo = 0x6F
+fuses_lo = 0xAF
 fuses_hi = 0x99
 fuses_ext = 0xff
 lock_byte = 0xff
diff --git a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm
index e04c42f..a991e01 100644
--- a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm
+++ b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm
@@ -1,7 +1,11 @@
+; VIDEO COMPOSITE PAL IO DEVICE
+; Implemented following timings in http://blog.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
+
 .include "atmega1284definition.asm"
 
 ; define constant
-.equ LED_PIN = PD7			; use PD7 as LED pin
+.equ SYNC_PIN = PD7		; Sync pin is on Port D 7 (pin 21)
+.equ VIDEO_PIN = PD6	; Video pin is on Port D 6 (pin 20)
 
 ; start vector
 .org 0x0000
@@ -9,23 +13,69 @@
 
 ; main program
 main:
-	sbi	DDRD, LED_PIN		; set LED pin as output
-loop:
-	sbic	PIND, LED_PIN		; if bit of LED pin is clear, skip next line
- 	cbi	PORTD, LED_PIN		; if 1, turn the LED off
-	sbis	PIND, LED_PIN		; if bit of LED pin is set, skip next line
- 	sbi	PORTD, LED_PIN		; if 0, light the LED up
-delay_500ms:
-	ldi	r20, 32			; set register, r20 = 32
-delay2:
-	ldi	r19, 64			; set register, r19 = 64
-delay1:
-	ldi	r18, 128		; set register, r18 = 128
-delay0:
-	dec	r18			; decrement register, r18 = r18 - 1
-	brne	delay0			; if r18 != 0, jump to label delay0
-	dec	r19			; decrement register, r19 = r19 -1
-	brne	delay1			; if r19 != 0, jump to label delay1
-	dec	r20			; decrement register, r20 = r20 -1
-	brne	delay2			; if r20 != 0, jump to label delay2
-	rjmp	loop			; if r20 == 0, jump to label loop
\ No newline at end of file
+	sbi	DDRD, SYNC_PIN		; set pin as output
+	sbi	DDRD, VIDEO_PIN		; set pin as output
+
+v_refresh_loop:
+	; start 5 long sync pulses
+
+	; end 5 long sync pulses
+
+	; start 5 short sync pulses
+
+	; end 5 short sync pulses
+
+	; start 304 picture lines
+	ldi r16, 2
+	h_picture_outer_loop:
+		ldi r17, 152	; line counter
+		h_picture_loop:
+			; start line sync: 4uS, 96 cycles @ 24Mhz
+			cbi	PORTD, SYNC_PIN	; sync goes low (0v)					; 2 cycle
+			ldi r18, 32													; 1 cycle
+			l_sync_pulse_loop: ; requires 3 cpu cycles
+				dec r18													; 1 cycle
+				brne l_sync_pulse_loop  								; 2 cycle if true, 1 if false
+			sbi	PORTD, SYNC_PIN	; sync goes high (0.3v)
+			; end line sync
+
+			; start back porch: 8uS, 192 cycles @ 24Mhz
+			ldi r18, 64													; 1 cycle
+			l_sync_back_porch_loop:
+				dec r18													; 1 cycle
+				brne l_sync_back_porch_loop  							; 2 cycle if true, 1 if false
+			; end back porch
+
+			; start image: 52uS, 1247 cycles @ 24Mhz
+			; 3 bande da 416 cicli
+
+			sbi	PORTD, VIDEO_PIN	; video goes high					; 2 cycle
+
+			ldi r18, 138													; 1 cycle
+			l_sync_video_loop1:
+				dec r18													; 1 cycle
+				brne l_sync_video_loop1  								; 2 cycle if true, 1 if false
+
+			cbi	PORTD, VIDEO_PIN	; video goes low
+
+			ldi r18, 137												; 1 cycle
+			l_sync_video_loop2:
+				dec r18													; 1 cycle
+				brne l_sync_video_loop2 								; 2 cycle if true, 1 if false
+
+			sbi	PORTD, VIDEO_PIN	; video goes high
+
+			ldi r18, 138												; 1 cycle
+			l_sync_video_loop3:
+				dec r18													; 1 cycle
+				brne l_sync_video_loop3  								; 2 cycle if true, 1 if false
+			cbi	PORTD, VIDEO_PIN	; video goes low
+
+			; end image
+
+			dec r17 ; decrement line counter
+			brne h_picture_loop	; if not 0, repeat h_picture_loop
+
+		dec r16 ; decrement outside counter
+		brne h_picture_outer_loop	; if not 0, repeat h_picture_loop
+	; end picture lines