diff --git a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/character_generator.asm b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/character_generator.asm new file mode 100644 index 0000000..d634ef2 --- /dev/null +++ b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/character_generator.asm @@ -0,0 +1,7 @@ +; ******************************************* +; * PAT80 COMPOSITE PAL VIDEO ADAPTER * +; * Character generator module * +; ******************************************* + +; This module generates the character pixels using the font present in rom +; and adds it on the framebuffer in the right position. diff --git a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/communication.asm b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/communication.asm new file mode 100644 index 0000000..34af32e --- /dev/null +++ b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/communication.asm @@ -0,0 +1,7 @@ +; ******************************************* +; * PAT80 COMPOSITE PAL VIDEO ADAPTER * +; * Communication module * +; ******************************************* + +; This module manages the communication between Pat80 and +; the video adapter. diff --git a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/cat.asm b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/example_data/cat.asm similarity index 100% rename from pat80-io-devices/composite-pal-adapter/software/avr-assembly/cat.asm rename to pat80-io-devices/composite-pal-adapter/software/avr-assembly/example_data/cat.asm diff --git a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/cat2.asm b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/example_data/cat2.asm similarity index 100% rename from pat80-io-devices/composite-pal-adapter/software/avr-assembly/cat2.asm rename to pat80-io-devices/composite-pal-adapter/software/avr-assembly/example_data/cat2.asm diff --git a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm index fe99b6a..41f9559 100644 --- a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm +++ b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm @@ -17,26 +17,19 @@ ; Sync pin: PC0 (pin 22) ; Debug hsync pin: PC1 (pin 23) ; -; STATUS TABLE: -; R25 (STATUS): Current status (what the interrupt should do when fired): -; 0-9 = long sync -; 10-19 = short sync -; 20 = draw lines (draw 304 lines complete with line sync and back porch, then start short -; sync: sync pin low and next interrupt after 2uS) -; 21-32 = short sync -; 33-255 = invalid state or screen draw finished: set to 0 and restart from first long sync start -.include "m1284def.inc" +.include "m1284def.inc" ; Atmega 1280 device definition +.include "video_generator.asm" ; Asyncronous timer-interrupt-based video generation +.include "character_generator.asm" ; Character generator +.include "communication.asm" ; Communication with Pat80 -; registers +; reserved registers .def A = r0 ; accumulator .def STATUS = r25 ; signal status (see STATUS TABLE) ; define constant .equ SYNC_PIN = PC0 ; Sync pin (pin 22) .equ DEBUG_PIN = PC1 ; DEBUG: Single vertical sync pulse to trigger oscilloscope (pin 23) -.equ TIMER_DELAY_30US = 65535 - 690 ; 719 cycles @ 24Mhz (minus overhead) -.equ TIMER_DELAY_2US = 65535 - 17 ; 48 cycles @ 24Mhz (minus overhead) ; memory .equ FRAMEBUFFER = 0x100 @@ -45,7 +38,7 @@ .org 0x0000 rjmp main ; reset vector: jump to main label .org 0x001E - rjmp on_tim1_ovf ; interrupt for timer 1 overflow + rjmp on_tim1_ovf ; interrupt for timer 1 overflow (used by video generation) .org 0x40 ; main program @@ -56,25 +49,6 @@ main: ldi r16, 0xFF out DDRA, r16 ; set port as output (contains video pin) - - ; *** Load data into ram *** - ; Set X to 0x0100 - ldi r27, high(FRAMEBUFFER<<1) - ldi r26, low(FRAMEBUFFER<<1) - ; Set Z to 0x1000 (cat image) - ldi r31, high(CAT_IMAGE<<1) - ldi r30, low(CAT_IMAGE<<1) - - load_mem_loop: - lpm r17, Z+ - ;ldi r17, 0b00001111 - st X+, r17 - ; if reached the last framebuffer byte, exit cycle - cpi r27, 0b00111110 - brne load_mem_loop ; if not 0, repeat h_picture_loop - cpi r26, 0b11000000 - brne load_mem_loop ; if not 0, repeat h_picture_loop - ; *** timer setup (use 16-bit counter TC1) *** ; The Power Reduction TC1 and TC3 bits in the Power Reduction Registers (PRR0.PRTIM1 and ; PRR1.PRTIM3) must be written to zero to enable the TC1 and TC3 module. @@ -93,1491 +67,3 @@ main: ; loop forever forever: jmp forever - - -; ********* FUNCTIONS CALLED BY INTERRUPT *********** -on_tim1_ovf: - ; debug - ; sbi PORTC, DEBUG_PIN ; high - ; cbi PORTC, DEBUG_PIN ; low - ; ; set timer in 30uS (reset timer counter) - ; ldi r27, high(TIMER_DELAY_30US) - ; ldi r26, low(TIMER_DELAY_30US) - ; sts TCNT1H,r27 - ; sts TCNT1L,r26 - ; reti - ; debug - - - - - - ; called by timer 1 two times per line (every 32 uS) during hsync, unless drawing picture. - inc STATUS - ; if STATUS >= 33 then STATUS=0 - cpi STATUS, 35 ; TODO: Added a seventh sync pulse at end of screen because at the first short sync after the image, the timer doesn't tick at the right time - brlo switch_status - clr STATUS - ; check status and decide what to do - switch_status: - cpi STATUS, 10 - brlo long_sync ; 0-9: long sync - cpi STATUS, 20 - breq draw_picture ; 20: draw picture - jmp short_sync ; 10-19 or 21-32: short_sync - ; reti is at end of all previous jumps - -draw_picture: - ; set X register to framebuffer start 0x0100 - ; (set it a byte before, because it will be incremented at first) - clr r27 - ldi r26, 0xFF - - ; start 304 picture lines - ldi r17, 152 ; line counter - h_picture_loop: - ; debug - ; sbi PORTC, DEBUG_PIN ; high - ; cbi PORTC, DEBUG_PIN ; low - ; debug - - ; ***************** DRAW FIRST LINE ********************* - - ; **** start line sync: 4uS, 96 cycles @ 24Mhz - ; video pin goes low before sync - clr r19 ; 1 cycle - out PORTA, r19 ; 1 cycle - - cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle - ldi r18, 31 ; 1 cycle - l_sync_pulse_loop: ; requires 3 cpu cycles - dec r18 ; 1 cycle - brne l_sync_pulse_loop ; 2 cycle if true, 1 if false - sbi PORTC, SYNC_PIN ; sync goes high (0.3v) - ; **** end line sync - - ; **** start line back porch: 8uS, 192 cycles @ 24Mhz - ; leave time at the end for line setup and draw_line call - ldi r18, 62 ; 1 cycle - l_sync_back_porch_loop: - dec r18 ; 1 cycle - brne l_sync_back_porch_loop ; 2 cycle if true, 1 if false - ; **** end back porch - - call draw_line ; 3 cycles (+ 3 to come back to on_line_drawn) - ; **** draws line pixels: 52uS, 1248 cycles @ 24Mhz **** - - - - ; ***************** DRAW SECOND LINE ********************* - - ; **** start line sync: 4uS, 96 cycles @ 24Mhz - ; video pin goes low before sync - clr r19 ; 1 cycle - out PORTA, r19 ; 1 cycle - - cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle - ldi r18, 31 ; 1 cycle - l_sync_pulse_loop2: ; requires 3 cpu cycles - dec r18 ; 1 cycle - brne l_sync_pulse_loop2 ; 2 cycle if true, 1 if false - sbi PORTC, SYNC_PIN ; sync goes high (0.3v) - ; **** end line sync - - ; **** start line back porch: 8uS, 192 cycles @ 24Mhz - ; leave time at the end for line setup and draw_line call - ldi r18, 62 ; 1 cycle - l_sync_back_porch_loop2: - dec r18 ; 1 cycle - brne l_sync_back_porch_loop2 ; 2 cycle if true, 1 if false - ; **** end back porch - - call draw_line ; 3 cycles (+ 3 to come back to on_line_drawn) - ; **** draws line pixels: 52uS, 1248 cycles @ 24Mhz **** - - - - - ; debug - ; sbi PORTC, DEBUG_PIN ; high - ; cbi PORTC, DEBUG_PIN ; low - ; debug - - dec r17 ; decrement line countr ; 1 cycle - brne h_picture_loop ; if not 0, repeat h_picture_loop ; 2 cycle if true, 1 if false - ; end picture lines - - ; video pin goes low before sync - clr r19 ; 1 cycle - out PORTA, r19 ; 1 cycle - - ; debug - ; sbi PORTC, DEBUG_PIN ; high - ; cbi PORTC, DEBUG_PIN ; low - ; debug - - - ; immediately start first end-screen short sync: - inc STATUS - jmp short_sync - ; reti is in short_sync -; end draw_picture - -long_sync: - ; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz) - - sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line - jmp long_sync_end - ; sync pin is high (sync is not occuring) - cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle - ; set timer in 30uS (reset timer counter) - ldi r27, high(TIMER_DELAY_30US) - ldi r26, low(TIMER_DELAY_30US) - sts TCNT1H,r27 - sts TCNT1L,r26 - reti - - long_sync_end: - ; sync pin is low (sync is occuring) - sbi PORTC, SYNC_PIN ; sync goes high (0.3v) - ; set timer in 2uS: - ldi r27, high(TIMER_DELAY_2US) - ldi r26, low(TIMER_DELAY_2US) - sts TCNT1H,r27 - sts TCNT1L,r26 - reti - - -short_sync: - ; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz) - - sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line - jmp short_sync_end - ; sync pin is high (sync is not occuring) - cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle - ; set timer in 2uS (reset timer counter) - ldi r27, high(TIMER_DELAY_2US) - ldi r26, low(TIMER_DELAY_2US) - sts TCNT1H,r27 - sts TCNT1L,r26 - reti - - short_sync_end: - ; sync pin is low (sync is occuring) - sbi PORTC, SYNC_PIN ; sync goes high (0.3v) - ; set timer in 30uS: - ldi r27, high(TIMER_DELAY_30US) - ldi r26, low(TIMER_DELAY_30US) - sts TCNT1H,r27 - sts TCNT1L,r26 - reti - - -draw_line: - ; NO loops, as this is time-strict - ; 52 chunks of 8 pixels - - ; chunk 1 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 2 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 3 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 4 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 5 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 6 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 7 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 8 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 9 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 10 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 11 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 12 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 13 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 14 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 15 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 16 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 17 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 18 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 19 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 20 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 21 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 22 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 23 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 24 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 25 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 26 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 27 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 28 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 29 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 30 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 31 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 32 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 33 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 34 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 35 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 36 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 37 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 38 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 39 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 40 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 41 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 42 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 43 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 44 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 45 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 46 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 47 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 48 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 49 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 50 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 51 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ; chunk 52 - ld A, X+ ; load pixel ; 2 cycles - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - nop ; 1 cycle - lsr A ; 1 cycle - out PORTA, A ; 1 cycle - - ret - - -.include "cat.asm" \ No newline at end of file diff --git a/pat80-io-devices/composite-pal-adapter/software/avr-assembly/video_generator.asm b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/video_generator.asm new file mode 100644 index 0000000..48ea734 --- /dev/null +++ b/pat80-io-devices/composite-pal-adapter/software/avr-assembly/video_generator.asm @@ -0,0 +1,1478 @@ +; ******************************************* +; * PAT80 COMPOSITE PAL VIDEO ADAPTER * +; * Video generator module * +; ******************************************* + +; This module generates a Composite PAL monochrome signal with a resolution +; of 416x304 pixels (= 52x38 characters). The signal is generated using 16-bit +; Timer1 and interrupts. + + +; How does it work: +; The screen draw is divided in phases. Every phase does something. I.e. phases 0 to 9 +; represents the first 5 long syncs: +; (sync goes low, wait 30uS, sync goes high, wait 2uS) x 5 times = 10 phases +; When the interrupt is called, it uses register r25 (STATUS) to decide what to do. +; +; STATUS TABLE: +; R25 (STATUS): Current status (what the interrupt should do when fired): +; 0-9 = long sync +; 10-19 = short sync +; 20 = draw lines (draw 304 lines complete with line sync and back porch, then start short +; sync: sync pin low and next interrupt after 2uS) +; 21-32 = short sync +; 33-255 = invalid state or screen draw finished: set to 0 and restart from first long sync start + +.equ TIMER_DELAY_30US = 65535 - 690 ; 719 cycles @ 24Mhz (minus overhead) +.equ TIMER_DELAY_2US = 65535 - 17 ; 48 cycles @ 24Mhz (minus overhead) + + +; ********* FUNCTIONS CALLED BY INTERRUPT *********** +on_tim1_ovf: + ; called by timer 1 two times per line (every 32 uS) during hsync, unless drawing picture. + inc STATUS + ; if STATUS >= 33 then STATUS=0 + cpi STATUS, 35 ; TODO: Added a seventh sync pulse at end of screen because at the first short sync after the image, the timer doesn't tick at the right time + brlo switch_status + clr STATUS + ; check status and decide what to do + switch_status: + cpi STATUS, 10 + brlo long_sync ; 0-9: long sync + cpi STATUS, 20 + breq draw_picture ; 20: draw picture + jmp short_sync ; 10-19 or 21-32: short_sync + ; reti is at end of all previous jumps + +draw_picture: + ; set X register to framebuffer start 0x0100 + ; (set it a byte before, because it will be incremented at first) + clr r27 + ldi r26, 0xFF + + ; start 304 picture lines + ldi r17, 152 ; line counter + h_picture_loop: + ; ***************** DRAW FIRST LINE ********************* + + ; **** start line sync: 4uS, 96 cycles @ 24Mhz + ; video pin goes low before sync + clr r19 ; 1 cycle + out PORTA, r19 ; 1 cycle + + cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle + ldi r18, 31 ; 1 cycle + l_sync_pulse_loop: ; requires 3 cpu cycles + dec r18 ; 1 cycle + brne l_sync_pulse_loop ; 2 cycle if true, 1 if false + sbi PORTC, SYNC_PIN ; sync goes high (0.3v) + ; **** end line sync + + ; **** start line back porch: 8uS, 192 cycles @ 24Mhz + ; leave time at the end for line setup and draw_line call + ldi r18, 62 ; 1 cycle + l_sync_back_porch_loop: + dec r18 ; 1 cycle + brne l_sync_back_porch_loop ; 2 cycle if true, 1 if false + ; **** end back porch + + call draw_line ; 3 cycles (+ 3 to come back to on_line_drawn) + ; **** draws line pixels: 52uS, 1248 cycles @ 24Mhz **** + + + + ; ***************** DRAW SECOND LINE ********************* + + ; **** start line sync: 4uS, 96 cycles @ 24Mhz + ; video pin goes low before sync + clr r19 ; 1 cycle + out PORTA, r19 ; 1 cycle + + cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle + ldi r18, 31 ; 1 cycle + l_sync_pulse_loop2: ; requires 3 cpu cycles + dec r18 ; 1 cycle + brne l_sync_pulse_loop2 ; 2 cycle if true, 1 if false + sbi PORTC, SYNC_PIN ; sync goes high (0.3v) + ; **** end line sync + + ; **** start line back porch: 8uS, 192 cycles @ 24Mhz + ; leave time at the end for line setup and draw_line call + ldi r18, 62 ; 1 cycle + l_sync_back_porch_loop2: + dec r18 ; 1 cycle + brne l_sync_back_porch_loop2 ; 2 cycle if true, 1 if false + ; **** end back porch + + call draw_line ; 3 cycles (+ 3 to come back to on_line_drawn) + ; **** draws line pixels: 52uS, 1248 cycles @ 24Mhz **** + + dec r17 ; decrement line countr ; 1 cycle + brne h_picture_loop ; if not 0, repeat h_picture_loop ; 2 cycle if true, 1 if false + ; end picture lines + + ; video pin goes low before sync + clr r19 ; 1 cycle + out PORTA, r19 ; 1 cycle + + ; immediately start first end-screen short sync: + inc STATUS + jmp short_sync + ; reti is in short_sync +; end draw_picture + +long_sync: + ; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz) + + sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line + jmp long_sync_end + ; sync pin is high (sync is not occuring) + cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle + ; set timer in 30uS (reset timer counter) + ldi r27, high(TIMER_DELAY_30US) + ldi r26, low(TIMER_DELAY_30US) + sts TCNT1H,r27 + sts TCNT1L,r26 + reti + + long_sync_end: + ; sync pin is low (sync is occuring) + sbi PORTC, SYNC_PIN ; sync goes high (0.3v) + ; set timer in 2uS: + ldi r27, high(TIMER_DELAY_2US) + ldi r26, low(TIMER_DELAY_2US) + sts TCNT1H,r27 + sts TCNT1L,r26 + reti + + +short_sync: + ; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz) + + sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line + jmp short_sync_end + ; sync pin is high (sync is not occuring) + cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle + ; set timer in 2uS (reset timer counter) + ldi r27, high(TIMER_DELAY_2US) + ldi r26, low(TIMER_DELAY_2US) + sts TCNT1H,r27 + sts TCNT1L,r26 + reti + + short_sync_end: + ; sync pin is low (sync is occuring) + sbi PORTC, SYNC_PIN ; sync goes high (0.3v) + ; set timer in 30uS: + ldi r27, high(TIMER_DELAY_30US) + ldi r26, low(TIMER_DELAY_30US) + sts TCNT1H,r27 + sts TCNT1L,r26 + reti + + +draw_line: + ; NO loops, as this is time-strict + ; 52 chunks of 8 pixels + + ; chunk 1 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 2 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 3 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 4 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 5 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 6 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 7 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 8 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 9 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 10 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 11 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 12 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 13 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 14 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 15 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 16 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 17 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 18 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 19 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 20 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 21 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 22 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 23 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 24 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 25 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 26 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 27 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 28 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 29 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 30 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 31 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 32 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 33 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 34 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 35 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 36 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 37 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 38 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 39 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 40 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 41 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 42 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 43 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 44 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 45 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 46 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 47 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 48 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 49 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 50 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 51 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ; chunk 52 + ld A, X+ ; load pixel ; 2 cycles + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + nop ; 1 cycle + lsr A ; 1 cycle + out PORTA, A ; 1 cycle + + ret