; *******************************************
; *    PAT80 COMPOSITE PAL VIDEO ADAPTER    *
; *        Video generator module           *
; *******************************************

; This module generates a Composite PAL monochrome signal with a resolution
; of 416x304 pixels (= 52x38 characters). The signal is generated using 16-bit
; Timer1 and interrupts.


; How does it work:
; The screen draw is divided in phases. Every phase does something. I.e. phases 0 to 9
; represents the first 5 long syncs:
; (sync goes low, wait 30uS, sync goes high, wait 2uS) x 5 times = 10 phases
; When the interrupt is called, it uses register r25 (STATUS) to decide what to do.
;
; STATUS TABLE:
; R25 (STATUS): Current status (what the interrupt should do when fired):
;	0-9 = long sync
;	10-19 = short sync
;	20 = draw lines (draw 304 lines complete with line sync and back porch, then start short
;		sync: sync pin low and next interrupt after 2uS)
;	21-32 = short sync
;	33-255 = invalid state or screen draw finished: set to 0 and restart from first long sync start

.equ TIMER_DELAY_30US = 65535 - 300 	; 333 cycles @ 11Mhz (minus overhead)
.equ TIMER_DELAY_2US = 65535 - 8		; 22 cycles @ 11Mhz (minus overhead)
.equ DURATION_DELAY_4US = 16		; 44 cycles @ 11Mhz
.equ DURATION_DELAY_8US = 88		; 88 cycles @ 11Mhz


; ********* FUNCTIONS CALLED BY INTERRUPT ***********
on_tim1_ovf:
	; TODO: save BUSY pin status and restore it before RETI, because it could be in BUSY status when interrupted
	; set BUSY pin to indicate the mc is unresponsive from now on
	sbi PORTD, BUSY_PIN
	; called by timer 1 two times per line (every 32 uS) during hsync, unless drawing picture.
	inc STATUS
	; if STATUS >= 33 then STATUS=0
	cpi STATUS, 35	; TODO: Added a seventh sync pulse at end of screen because at the first short sync after the image, the timer doesn't tick at the right time
	brlo switch_status
	clr STATUS
	; check status and decide what to do
	switch_status:
		cpi STATUS, 10
		brlo long_sync	; 0-9: long sync
		cpi STATUS, 20
		breq draw_picture ; 20: draw picture
		jmp short_sync  ; 10-19 or 21-32: short_sync
	; reti is at end of all previous jumps

draw_picture:
	; save X register
	push XH
	push XL

	; set X register to framebuffer start 0x0100
	; (set it a byte before, because it will be incremented at first)
	ldi r27, high(FRAMEBUFFER - 1)
	ldi r26, low(FRAMEBUFFER - 1)

	; start 32 empty picture lines (back porch)
	ldi LINE_COUNTER, 32	; line counter
	back_porch_picture_loop:
		call draw_empty_line	; 3 cycles (+ 3 to come back)
		dec LINE_COUNTER ; decrement line countr					; 1 cycle
		brne back_porch_picture_loop	; if not 0, repeat h_picture_loop		; 2 cycle if true, 1 if false
	; end picture lines

	; start 240 picture lines
	ldi LINE_COUNTER, 240	; line counter
	h_picture_loop:
		call draw_line	; 3 cycles (+ 3 to come back to on_line_drawn)
		dec LINE_COUNTER ; decrement line countr					; 1 cycle
		brne h_picture_loop	; if not 0, repeat h_picture_loop		; 2 cycle if true, 1 if false
	; end picture lines

	; start 32 empty picture lines (front porch)
	ldi LINE_COUNTER, 32	; line counter
	front_porch_picture_loop:
		call draw_empty_line	; 3 cycles (+ 3 to come back)
		dec LINE_COUNTER ; decrement line countr					; 1 cycle
		brne front_porch_picture_loop	; if not 0, repeat h_picture_loop		; 2 cycle if true, 1 if false
	; end picture lines

	; restore X register
	pop XL
	pop XH

	; video pin goes low before sync
	clr VG_HIGH_ACCUM											; 1 cycle
	out VIDEO_PORT_OUT, VG_HIGH_ACCUM							; 1 cycle

	; immediately start first end-screen short sync:
	inc STATUS
	jmp short_sync
	; reti is in short_sync
; end draw_picture

long_sync:
	; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz)

	sbis PORTC, SYNC_PIN	; if sync is high (sync is not occuring) skip next line
	jmp long_sync_end
	; sync pin is high (sync is not occuring)
	cbi	PORTC, SYNC_PIN	; sync goes low (0v)					; 2 cycle
	; set timer in 30uS (reset timer counter)
	ldi r27, high(TIMER_DELAY_30US)
	ldi r26, low(TIMER_DELAY_30US)
	sts	TCNT1H,r27
	sts	TCNT1L,r26
	; clear BUSY pin to indicate the mc is again responsive from now on
	cbi PORTD, BUSY_PIN
	reti

	long_sync_end:
		; sync pin is low (sync is occuring)
		sbi	PORTC, SYNC_PIN	; sync goes high (0.3v)
		; set timer in 2uS:
		ldi r27, high(TIMER_DELAY_2US)
		ldi r26, low(TIMER_DELAY_2US)
		sts	TCNT1H,r27
		sts	TCNT1L,r26
		; clear BUSY pin to indicate the mc is again responsive from now on
		cbi PORTD, BUSY_PIN
		reti


short_sync:
	; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz)

	sbis PORTC, SYNC_PIN	; if sync is high (sync is not occuring) skip next line
	jmp short_sync_end
	; sync pin is high (sync is not occuring)
	cbi	PORTC, SYNC_PIN	; sync goes low (0v)					; 2 cycle
	; set timer in 2uS (reset timer counter)
	ldi r27, high(TIMER_DELAY_2US)
	ldi r26, low(TIMER_DELAY_2US)
	sts	TCNT1H,r27
	sts	TCNT1L,r26
	; clear BUSY pin to indicate the mc is again responsive from now on
	cbi PORTD, BUSY_PIN
	reti

	short_sync_end:
		; sync pin is low (sync is occuring)
		sbi	PORTC, SYNC_PIN	; sync goes high (0.3v)
		; set timer in 30uS:
		ldi r27, high(TIMER_DELAY_30US)
		ldi r26, low(TIMER_DELAY_30US)
		sts	TCNT1H,r27
		sts	TCNT1L,r26
		; clear BUSY pin to indicate the mc is again responsive from now on
		cbi PORTD, BUSY_PIN
		reti


draw_line:
	; **** start line sync: 4uS, 16 cycles @ 11Mhz
	; video pin goes low before sync
	clr VG_HIGH_ACCUM										; 1 cycle
	out VIDEO_PORT_OUT, VG_HIGH_ACCUM						; 1 cycle

	cbi	PORTC, SYNC_PIN	; sync goes low (0v)					; 2 cycle
	ldi VG_HIGH_ACCUM, DURATION_DELAY_4US/3						; 1 cycle
	l_sync_pulse_loop: ; requires 3 cpu cycles
		dec VG_HIGH_ACCUM									; 1 cycle
		brne l_sync_pulse_loop  								; 2 cycle if true, 1 if false
	sbi	PORTC, SYNC_PIN	; sync goes high (0.3v)
	; **** end line sync

	; **** start line back porch: 8uS, 192 cycles @ 24Mhz
	; leave time at the end for line setup and draw_line call
	ldi VG_HIGH_ACCUM, DURATION_DELAY_8US/3									; 1 cycle
	l_sync_back_porch_loop:
		dec VG_HIGH_ACCUM									; 1 cycle
		brne l_sync_back_porch_loop  							; 2 cycle if true, 1 if false
	; **** end back porch

	; 64 chunks of 8 pixels
	ldi VG_HIGH_ACCUM, 64			; 1 cycle
	draw_chunk: ; requires 8 cpu cycles
		ld A, X+	; load chunk	; 2 cycles
		out VIDEO_PORT_OUT, A		; 1 cycle
		; TODO: A posto di questi due NOP ci andrebbe un cbi e un sbi per far caricare allo shift register il byte
		nop							; 1 cycle
		nop							; 1 cycle
		dec VG_HIGH_ACCUM			; 1 cycle
		brne draw_chunk  			; 2 cycle if true, 1 if false
	ret

draw_empty_line:
	; video pin goes low before sync
	clr VG_HIGH_ACCUM										; 1 cycle
	out VIDEO_PORT_OUT, VG_HIGH_ACCUM						; 1 cycle

	cbi	PORTC, SYNC_PIN	; sync goes low (0v)					; 2 cycle
	ldi VG_HIGH_ACCUM, DURATION_DELAY_4US/3						; 1 cycle
	l_sync_pulse_loop: ; requires 3 cpu cycles
		dec VG_HIGH_ACCUM									; 1 cycle
		brne l_sync_pulse_loop  								; 2 cycle if true, 1 if false
	sbi	PORTC, SYNC_PIN	; sync goes high (0.3v)
	; **** end line sync

	; an empty line: 60 uS of black
	clr A						; 1 cycle
	out VIDEO_PORT_OUT, A		; 1 cycle
	ldi VG_HIGH_ACCUM, 666/3	; 1 cycle
	draw_empty_line_loop: ; requires 3 cycles
		dec VG_HIGH_ACCUM			; 1 cycle
		brne draw_chunk  			; 2 cycle if true, 1 if false
	ret