initial commit.
This commit is contained in:
Chris Burbridge
73
fuse_tests/README
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73
fuse_tests/README
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File formats
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============
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tests.in
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--------
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Each test has the format:
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<arbitrary test description>
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AF BC DE HL AF' BC' DE' HL' IX IY SP PC
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I R IFF1 IFF2 IM <halted> <tstates>
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<halted> specifies whether the Z80 is halted.
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<tstates> specifies the number of tstates to run the test for, in
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decimal; the number actually executed may be higher, as the final
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instruction is allowed to complete.
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Then followed by lines specifying the initial memory setup. Each has
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the format:
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<start address> <byte1> <byte2> ... -1
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eg
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1234 56 78 9a -1
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says to put 0x56 at 0x1234, 0x78 at 0x1235 and 0x9a at 0x1236.
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Finally, -1 to end the test. Blank lines may follow before the next test.
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tests.expected
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--------------
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Each test output starts with the test description, followed by a list
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of 'events': each has the format
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<time> <type> <address> <data>
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<time> is simply the time at which the event occurs.
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<type> is one of MR (memory read), MW (memory write), MC (memory
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contend), PR (port read), PW (port write) or PC (port contend).
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<address> is the address (or IO port) affected.
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<data> is the byte written or read. Missing for contentions.
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After that, lines specifying AF, BC etc as for .in files. <tstates>
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now specifies the final time.
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After that, lines specifying which bits of memory have changed since
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the initial setup. Same format as for .in files.
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Why some specific tests are here
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================================
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37_{1,2,3}: check the behaviour of SCF with respect to bits 3 and 5
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(bug fixed on 20040225).
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cb{4,5,6,7}{7,f}_1: designed to check that bits 3 and 5 are copied to
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F only for BIT 3,<arg> and BIT 5,<arg> respectively
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(bug fixed on 20040225).
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However, later research has revealed the bits 3
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and 5 are copied on all BIT instructions, l.
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tests are now essentially redundant.
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d{3,b}_{1,2,3}: check for correct port contention on IO in the four
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relevant states (port high byte in 0x40 to 0x7f or not,
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port low bit set or reset).
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dd00.in, ddfd00.in: test timings of "extended NOP" opcodes DD 00 and
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DD FD 00; the extra 00 at the end is to check the
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next opcode executes at the right time (bug fixed
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on 20060722).
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18395
fuse_tests/tests.expected
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18395
fuse_tests/tests.expected
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File diff suppressed because it is too large
Load Diff
9011
fuse_tests/tests.in
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9011
fuse_tests/tests.in
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File diff suppressed because it is too large
Load Diff
267
fuse_tests/tests.py
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267
fuse_tests/tests.py
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from z80 import io, gui, instructions, registers, util
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import copy
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from time import sleep, time
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import sys
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from PySide.QtCore import *
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from PySide.QtGui import *
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import threading
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import os
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import inspect
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#logging.basicConfig(level=logging.INFO)
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class Z80Tester(io.Interruptable):
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def __init__(self):
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self.registers = registers.Registers()
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self.instructions = instructions.InstructionSet(self.registers)
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self._memory = bytearray(64*1024)
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self._interrupted = False
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def interrupt(self):
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self._interrupted = True
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def step_instruction(self):
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trace = ""
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ins, args = False, []
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pc = self.registers.PC
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if self._interrupted and self.registers.IFF:
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self.registers.IFF = False
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self._interrupted = False
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if self.registers.IM == 1:
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print "!!! Interrupt !!!"
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ins, args = self.instructions << 0xCD
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ins, args = self.instructions << 0x38
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ins, args = self.instructions << 0x00
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self.registers.IFF = False
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else:
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while not ins:
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try:
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ins, args = self.instructions << self._memory[self.registers.PC]
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except:
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raise Exception("Can't decode instruction.")
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self.registers.PC = util.inc16(self.registers.PC)
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trace += "{0:X} : {1}\n ".format(pc, ins.assembler(args))
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rd = ins.get_read_list(args)
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data = [0] * len(rd)
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for n, i in enumerate(rd):
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if i < 0x10000:
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data[n] = self._memory[i]
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else:
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address = i & 0xFF
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#data[n] = self._iomap.address[address].read(address)
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data[n] = self.registers.A
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print "Read IO ",
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raise Exception("Skip.")
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wrt = ins.execute(data, args)
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for i in wrt:
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if i[0] > 0x10000:
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address = i[0] & 0xFF
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#iomap.address[address].write.emit(address, i[1])
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#self._iomap.address[address].write(address, i[1])
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#print (chr(i[1]))
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print "Write IO ",
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raise Exception("Skip.")
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else:
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try:
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self._memory[i[0]] = i[1]
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except:
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print i
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print trace
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raise
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return ins.tstates, trace
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if __name__ == '__main__':
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''' Main Program '''
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mach = Z80Tester()
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infile = file = os.path.join(os.path.dirname(os.path.abspath(inspect.getfile(inspect.currentframe()))),
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"tests.in")
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expectfile = file = os.path.join(os.path.dirname(os.path.abspath(inspect.getfile(inspect.currentframe()))),
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"tests.expected")
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with open(infile, "r") as f:
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tests_in = f.read()
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with open(expectfile, "r") as f:
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tests_expected = f.read()
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fails = passes = 0
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for t, results in zip(tests_in.split("\n\n"), tests_expected.split("\n\n")):
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#print "---\n", t, "\n====\n", results,"\n---\n"
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test_lines = t.split("\n")
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test_key = test_lines[0]
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regs = [int(s, 16) for s in test_lines[1].split()]
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mach.registers.AF = regs[0]
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mach.registers.BC = regs[1]
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mach.registers.DE = regs[2]
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mach.registers.HL = regs[3]
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mach.registers.A_ = regs[4] >> 8
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mach.registers.F_ = regs[4] & 0xFF
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mach.registers.B_ = regs[5] >> 8
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mach.registers.C_ = regs[5] & 0xFF
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mach.registers.D_ = regs[6] >> 8
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mach.registers.E_ = regs[6] & 0xFF
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mach.registers.H_ = regs[7] >> 8
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mach.registers.L_ = regs[7] & 0xFF
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mach.registers.IX = regs[8]
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mach.registers.IY = regs[9]
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mach.registers.SP = regs[10]
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mach.registers.PC = regs[11]
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regs2 = [s for s in test_lines[2].split()]
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mach.registers.I = int(regs2[0], 16)
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mach.registers.R = int(regs2[1], 16)
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mach.registers.IFF = regs2[2] == "1"
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mach.registers.IFF2 = regs2[3] == "1"
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mach.registers.IFF2 = regs2[3] == "1"
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mach.registers.IM = regs2[4] == "1"
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mach.registers.HALT = regs2[5] == "1"
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tstates = int(regs2[6])
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for memline in test_lines[3:]:
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memsplit = memline.split()
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base = int(memsplit[0], 16)
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for val in memsplit[1:-1]:
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if int(val, 16) == -1:
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continue
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mach._memory[base] = int(val, 16)
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base += 1
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print ": Test '%s' : "%(str(test_key)),
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if test_key.startswith("27"):
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print "SKIPPED"
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continue
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trace = ""
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taken= 0
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try:
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while taken < tstates:
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states, asm = mach.step_instruction()
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taken += states
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trace += "%d/%d\t%d\t" % (taken, tstates, states) + asm
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except Exception, e:
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if e.message == "Can't decode instruction.":
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print " - NO INSTRUCTION"
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mach.instructions.reset_composer()
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continue
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elif e.message == "Skip.":
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print "Skipped."
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mach.instructions.reset_composer()
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continue
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else:
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print "FAULTY"
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mach.instructions.reset_composer()
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raise
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expected_lines = results.split('\n')
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if expected_lines[0] != test_key:
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print "Test expectation mismatch"
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sys.exit(1)
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i = 1
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while expected_lines[i].startswith(" "):
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i += 1
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regs = [int(s, 16) for s in expected_lines[i].split()]
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try:
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if mach.registers.A != regs[0] >> 8:
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raise Exception("Bad A register")
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if mach.registers.BC != regs[1]:
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raise Exception("Bad register")
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if mach.registers.DE != regs[2]:
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raise Exception("Bad register")
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if mach.registers.HL != regs[3]:
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raise Exception("Bad register")
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if mach.registers.A_ != regs[4] >> 8:
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raise Exception("Bad register")
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if mach.registers.F_ != regs[4] & 0xFF:
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raise Exception("Bad register")
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if mach.registers.B_ != regs[5] >> 8:
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raise Exception("Bad register")
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if mach.registers.C_ != regs[5] & 0xFF:
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raise Exception("Bad register")
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if mach.registers.D_ != regs[6] >> 8:
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raise Exception("Bad register")
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if mach.registers.E_ != regs[6] & 0xFF:
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raise Exception("Bad register")
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if mach.registers.H_ != regs[7] >> 8:
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raise Exception("Bad register")
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if mach.registers.L_ != regs[7] & 0xFF:
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raise Exception("Bad register")
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if mach.registers.IX != regs[8]:
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raise Exception("Bad register")
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if mach.registers.IY != regs[9]:
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raise Exception("Bad register")
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if mach.registers.SP != regs[10]:
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raise Exception("Bad register")
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if mach.registers.PC != regs[11]:
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raise Exception("Bad register")
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regs2 = [s for s in expected_lines[i+1].split()]
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if mach.registers.I != int(regs2[0], 16):
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raise Exception("Bad register")
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#if mach.registers.R != regs2[1]:
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#raise Exception("Bad register")
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if mach.registers.IFF != (regs2[2] == "1"):
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print "Bad interrups flag flop"
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print regs2[2]
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print mach.registers.IFF
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raise Exception("Bad register")
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if mach.registers.IFF2 != (regs2[3] == "1"):
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print "Bad interrups flag flop"
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print regs2[3]
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print mach.registers.IFF2
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raise Exception("Bad register")
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#if mach.registers.IFF2 != (regs2[3] == "1"):
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#raise Exception("Bad register")
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if mach.registers.IM != int(regs2[4]):
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raise Exception("Bad register")
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if mach.registers.HALT != (regs2[5] == "1"):
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raise Exception("Bad HALT register. "+str(mach.registers.HALT)+"!="+ str(regs2[5]=='1'))
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if taken != int(regs2[6]):
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raise Exception("Bad number of tstates taken.")
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if mach.registers.F != regs[0] & 0xFF:
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raise Exception("Bad F register")
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for memline in expected_lines[i+3:]:
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memsplit = memline.split()
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base = int(memsplit[0], 16)
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for val in memsplit[1:-1]:
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if int(val, 16) == -1:
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continue
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if mach._memory[base] != int(val, 16):
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raise Exception("Memory mismatch")
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base += 1
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except Exception, e:
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print "FAILED:",e.message
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fails += 1
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continue
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print "TRACE:"
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print trace
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print
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flags = ["S", "Z", "F5", "H", "F3", "PV", "N", "C"]
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s = ""
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for i, f in enumerate(flags):
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s += f+':' + str((regs[0] >> (7 - i)) & 0x01) + ' '
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print "\nTarget flags: ", s
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s = ""
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for i, f in enumerate(flags):
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s += f+':' + str((mach.registers.F >> (7 - i)) & 0x01) + ' '
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print "Actual flags: ", s
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print
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print "--INITIAL--\n", t, "\n--TARGET--\n", results,"\n==--==\n"
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regs = ['PC', 'SP', 'I',
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'A', 'F', 'B', 'C',
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'D', 'E', 'H', 'L',
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'IFF']
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regsr = ['IX', 'IY', 'R','A_', 'F_', 'B_', 'C_','D_', 'E_','H_', 'L_', 'IM']
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print "Registers:"
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for rl, rr in zip(regs, regsr):
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print rl, ": {0:X}".format( mach.registers[rl]), "\t\t", rr, ": {0:X}".format( mach.registers[rr])
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raise
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print "PASSED"
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passes += 1
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print "Failed:", fails
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print "Passed:", passes
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