From 89fd52113a1d9067852d7a80f50030e36a115ea7 Mon Sep 17 00:00:00 2001 From: Daniele Verducci Date: Wed, 25 May 2022 23:26:49 +0200 Subject: [PATCH] Ported to Python3 --- fuse_tests/tests.py | 71 +++++++++++++++++++++-------------------- src/z80/gui.py | 13 ++++---- src/z80/instructions.py | 12 +++---- src/z80/io.py | 11 ++++--- src/z80/registers.py | 2 +- src/z80/util.py | 4 +-- src/z80sbc.py | 9 +++--- 7 files changed, 63 insertions(+), 59 deletions(-) diff --git a/fuse_tests/tests.py b/fuse_tests/tests.py index e3b54fa..eb12bc8 100644 --- a/fuse_tests/tests.py +++ b/fuse_tests/tests.py @@ -3,8 +3,8 @@ import copy from time import sleep, time import sys -from PySide.QtCore import * -from PySide.QtGui import * +from PySide2.QtCore import * +from PySide2.QtGui import * import threading import os @@ -32,7 +32,7 @@ class Z80Tester(io.Interruptable): self.registers.IFF = False self._interrupted = False if self.registers.IM == 1: - print "!!! Interrupt !!!" + print ("!!! Interrupt !!!") ins, args = self.instructions << 0xCD ins, args = self.instructions << 0x38 ins, args = self.instructions << 0x00 @@ -55,7 +55,7 @@ class Z80Tester(io.Interruptable): address = i & 0xFF #data[n] = self._iomap.address[address].read(address) data[n] = self.registers.A - print "Read IO ", + print ("Read IO "), raise Exception("Skip.") wrt = ins.execute(data, args) for i in wrt: @@ -65,14 +65,14 @@ class Z80Tester(io.Interruptable): #iomap.address[address].write.emit(address, i[1]) #self._iomap.address[address].write(address, i[1]) #print (chr(i[1])) - print "Write IO ", + print ("Write IO "), raise Exception("Skip.") else: try: self._memory[i[0]] = i[1] except: - print i - print trace + print (i) + print (trace) raise return ins.tstates, trace @@ -131,9 +131,9 @@ if __name__ == '__main__': base += 1 - print ": Test '%s' : "%(str(test_key)), + print (": Test '%s' : "%(str(test_key))), if test_key.startswith("27"): - print "SKIPPED" + print ("SKIPPED") continue trace = "" taken= 0 @@ -142,23 +142,23 @@ if __name__ == '__main__': states, asm = mach.step_instruction() taken += states trace += "%d/%d\t%d\t" % (taken, tstates, states) + asm - except Exception, e: - if e.message == "Can't decode instruction.": - print " - NO INSTRUCTION" + except Exception as e: + if e == "Can't decode instruction.": + print (" - NO INSTRUCTION") mach.instructions.reset_composer() continue - elif e.message == "Skip.": - print "Skipped." + elif e == "Skip.": + print ("Skipped.") mach.instructions.reset_composer() continue else: - print "FAULTY" + print ("FAULTY") mach.instructions.reset_composer() raise expected_lines = results.split('\n') if expected_lines[0] != test_key: - print "Test expectation mismatch" + print ("Test expectation mismatch") sys.exit(1) i = 1 while expected_lines[i].startswith(" "): @@ -203,14 +203,14 @@ if __name__ == '__main__': #if mach.registers.R != regs2[1]: #raise Exception("Bad register") if mach.registers.IFF != (regs2[2] == "1"): - print "Bad interrups flag flop" - print regs2[2] - print mach.registers.IFF + print ("Bad interrups flag flop") + print (regs2[2]) + print (mach.registers.IFF) raise Exception("Bad register") if mach.registers.IFF2 != (regs2[3] == "1"): - print "Bad interrups flag flop" - print regs2[3] - print mach.registers.IFF2 + print ("Bad interrups flag flop") + print (regs2[3]) + print (mach.registers.IFF2) raise Exception("Bad register") #if mach.registers.IFF2 != (regs2[3] == "1"): #raise Exception("Bad register") @@ -233,35 +233,36 @@ if __name__ == '__main__': if mach._memory[base] != int(val, 16): raise Exception("Memory mismatch") base += 1 - except Exception, e: - print "FAILED:",e.message + except Exception as e: + print ("FAILED:",e.message) fails += 1 continue - print "TRACE:" - print trace - print + print ("TRACE:") + print (trace) + print ("") flags = ["S", "Z", "F5", "H", "F3", "PV", "N", "C"] s = "" for i, f in enumerate(flags): s += f+':' + str((regs[0] >> (7 - i)) & 0x01) + ' ' - print "\nTarget flags: ", s + print ("\nTarget flags: ", s) s = "" for i, f in enumerate(flags): s += f+':' + str((mach.registers.F >> (7 - i)) & 0x01) + ' ' - print "Actual flags: ", s + print ("Actual flags: ", s) print - print "--INITIAL--\n", t, "\n--TARGET--\n", results,"\n==--==\n" + print ("--INITIAL--\n", t, "\n--TARGET--\n", results,"\n==--==\n") regs = ['PC', 'SP', 'I', 'A', 'F', 'B', 'C', 'D', 'E', 'H', 'L', 'IFF'] regsr = ['IX', 'IY', 'R','A_', 'F_', 'B_', 'C_','D_', 'E_','H_', 'L_', 'IM'] - print "Registers:" + print ("Registers:") for rl, rr in zip(regs, regsr): - print rl, ": {0:X}".format( mach.registers[rl]), "\t\t", rr, ": {0:X}".format( mach.registers[rr]) + print (rl, ": {0:X}".format( mach.registers[rl]), "\t\t", rr, ": {0:X}".format( mach.registers[rr])) raise - print "PASSED" + print ("PASSED") passes += 1 - print "Failed:", fails - print "Passed:", passes \ No newline at end of file + print ("Failed:", fails) + print ("Passed:", passes) + print ("Passed:", passes) \ No newline at end of file diff --git a/src/z80/gui.py b/src/z80/gui.py index a4da213..10cbb7d 100644 --- a/src/z80/gui.py +++ b/src/z80/gui.py @@ -1,10 +1,11 @@ import sys -from PySide.QtCore import * -from PySide.QtGui import * -from PySide.QtWebKit import * +from PySide2.QtCore import * +from PySide2.QtGui import * +from PySide2.QtWidgets import * +from PySide2.QtWebEngineWidgets import * -from cStringIO import StringIO +from io import StringIO class RegistersGUI(QWidget): _addresses = [0x80, 0x81] @@ -136,7 +137,7 @@ class RegistersGUI(QWidget): vbox=QVBoxLayout() self.setLayout(vbox) - self._view = QWebView() + self._view = QWebEngineView(self) vbox.addWidget(self._view) @@ -179,7 +180,7 @@ class MemoryView(QWidget): self._memory = memory self._registers = registers self._update_sgl.connect(self._update) - self._web_view = QWebView() + self._web_view = QWebEngineView(self) vbox = QVBoxLayout() self.setLayout(vbox) diff --git a/src/z80/instructions.py b/src/z80/instructions.py index 19349c8..0c69de5 100644 --- a/src/z80/instructions.py +++ b/src/z80/instructions.py @@ -1,6 +1,6 @@ import copy import logging -from util import * +from . util import * import sys class instruction(object): @@ -63,9 +63,9 @@ class InstructionSet(): for i in dir(self): f = getattr(self, i) if f.__class__ == Instruction: - print i, ":" + print (i, ":") for o in f.opcode_args: - print o + print (o) ff = copy.copy(f) ff.registers = self._registers ff.args = o[1] @@ -86,7 +86,7 @@ class InstructionSet(): else: opargs = ((o[0], ), o[1]) for n, i in enumerate(opargs[0][:-1]): - if d.has_key(i): + if i in d: d = d[i] elif i == "-": ff.operands.append(n) @@ -120,7 +120,7 @@ class InstructionSet(): if self.is_two_parter(ins): return self._instructions[ins] else: - if self._instructions[0].has_key(ins): + if ins in self._instructions[0]: return self._instructions[0][ins] raise AttributeError("Unknown opcode") @@ -141,7 +141,7 @@ class InstructionSet(): self._instruction_composer = [] def is_two_parter(self, ins): - return self._instructions.has_key(ins) + return ins in self._instructions #---------------------------------------------------------------------- diff --git a/src/z80/io.py b/src/z80/io.py index a055c92..74aa3f2 100644 --- a/src/z80/io.py +++ b/src/z80/io.py @@ -1,7 +1,8 @@ import sys -from PySide.QtCore import * -from PySide.QtGui import * +from PySide2.QtCore import * +from PySide2.QtGui import * +from PySide2.QtWidgets import * class IO(object): _addresses = [] @@ -12,7 +13,7 @@ class IO(object): class Interruptable(object): def interrupt(self): - print "interrupt" + print ("interrupt") pass class Console(QTextEdit, IO): @@ -35,7 +36,7 @@ class Console(QTextEdit, IO): self._send_queue = None def read(self, address): - print "READ ", address + print ("READ ", address) if address == 0x80: v = ((1 << 1) | # RTS ((self._send_queue is not None) << 0) | # interrupt? @@ -51,7 +52,7 @@ class Console(QTextEdit, IO): @Slot(int, int) def write(self, address, value): - print "------> WRITE ", address + print ("------> WRITE ", address) self._wrt_sgnl.emit(address, value) def _write(self, address, value): diff --git a/src/z80/registers.py b/src/z80/registers.py index 1689a59..c660810 100644 --- a/src/z80/registers.py +++ b/src/z80/registers.py @@ -68,7 +68,7 @@ class Registers(dict): self[attr] = val def __getattr__(self, reg): - if self.has_key(reg): + if reg in self: return self[reg] elif reg in ["HL", "AF", "BC", "DE"]: return self[reg[0]] << 8 | self[reg[1]] diff --git a/src/z80/util.py b/src/z80/util.py index 45bf15d..f887cae 100644 --- a/src/z80/util.py +++ b/src/z80/util.py @@ -105,7 +105,7 @@ def add8(a, b, registers, S=True, Z=True, H=True, def add16(a, b, registers): """ add a and b, return result and set flags """ res = a + b - print a, "+",b,"=",res + print (a, "+",b,"=",res) registers.condition.S = (res >> 15) & 0x01 registers.condition.Z = (res == 0) if ((a & 0xFFF) + (b & 0xFFF)) > 0xFFF : @@ -126,7 +126,7 @@ def add16(a, b, registers): def subtract16(a, b, registers): """ subtract b from a, return result and set flags """ res = a - b - print a, "-", b, "=", res, "(", hex(res), ")" + print (a, "-", b, "=", res, "(", hex(res), ")") registers.condition.S = (res >> 15) & 0x01 registers.condition.N = 1 registers.condition.Z = (res == 0) diff --git a/src/z80sbc.py b/src/z80sbc.py index e61dd52..93fed85 100644 --- a/src/z80sbc.py +++ b/src/z80sbc.py @@ -4,8 +4,9 @@ import copy from time import sleep, time import sys -from PySide.QtCore import * -from PySide.QtGui import * +from PySide2.QtCore import * +from PySide2.QtGui import * +from PySide2.QtWidgets import * import threading @@ -58,7 +59,7 @@ class Z80SBC(io.Interruptable): self.registers.IFF = False self._interrupted = False if self.registers.IM == 1: - print "!!! Interrupt !!!" + print ("!!! Interrupt !!!") ins, args = self.instructions << 0xCD ins, args = self.instructions << 0x38 ins, args = self.instructions << 0x00 @@ -102,7 +103,7 @@ if __name__ == '__main__': while True: # t = time() ins, args = mach.step_instruction() - print ins.assembler(args) + print (ins.assembler(args)) sleep(0.00000001) # print (time() - t) / ins.tstates