2021-01-19 08:36:01 +01:00
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; *******************************************
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; * PAT80 COMPOSITE PAL VIDEO ADAPTER *
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; * Communication module *
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; *******************************************
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; This module manages the communication between Pat80 and
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; the video adapter.
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2021-01-19 20:55:11 +01:00
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; The data port is PORTB. The CLK (clock) signal is on PORTD0
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; and the RS (register select) on PORTD1
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; Initializes and waits for a byte on PORTB
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comm_init:
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; Set Z to framebuffer start
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ldi r31, high(FRAMEBUFFER<<1)
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ldi r30, low(FRAMEBUFFER<<1)
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comm_wait_byte:
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in r24, PINB ; read PORTB
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; Check continuously CLK until a LOW is found
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sbic PORTD, CLK_PIN
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jmp comm_wait_byte
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; CLK triggered: Copy PORTB to the next framebuffer byte
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st Z+, r24
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; if reached the last framebuffer byte, exit cycle
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cpi r31, 0b00111110
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brne comm_wait_byte ; if not 0, repeat h_picture_loop
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cpi r30, 0b11000000
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brne comm_wait_byte ; if not 0, repeat h_picture_loop
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jmp comm_init ; filled all memory: reset framebuffer position
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