88 lines
2.8 KiB
Plaintext
88 lines
2.8 KiB
Plaintext
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<project source="2.7.1" version="1.0">
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This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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<lib desc="#Wiring" name="0"/>
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<lib desc="#Gates" name="1">
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<tool name="NAND Gate">
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<a name="size" val="30"/>
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<a name="inputs" val="2"/>
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</tool>
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</lib>
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<lib desc="#Plexers" name="2"/>
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<lib desc="#Arithmetic" name="3"/>
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<lib desc="#Memory" name="4"/>
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<lib desc="#I/O" name="5"/>
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<lib desc="#Base" name="6">
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<tool name="Text Tool">
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<a name="text" val=""/>
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<a name="font" val="SansSerif plain 12"/>
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<a name="halign" val="center"/>
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<a name="valign" val="base"/>
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</tool>
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</lib>
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<main name="main"/>
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<options>
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<a name="gateUndefined" val="ignore"/>
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<a name="simlimit" val="1000"/>
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<a name="simrand" val="0"/>
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</options>
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<mappings>
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<tool lib="6" map="Button2" name="Menu Tool"/>
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<tool lib="6" map="Button3" name="Menu Tool"/>
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<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
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</mappings>
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<toolbar>
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<tool lib="6" name="Poke Tool"/>
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<tool lib="6" name="Edit Tool"/>
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<tool lib="6" name="Text Tool">
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<a name="text" val=""/>
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<a name="font" val="SansSerif plain 12"/>
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<a name="halign" val="center"/>
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<a name="valign" val="base"/>
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</tool>
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<sep/>
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<tool lib="0" name="Pin">
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<a name="tristate" val="false"/>
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</tool>
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<tool lib="0" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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<a name="labelloc" val="east"/>
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</tool>
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<tool lib="1" name="NOT Gate"/>
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<tool lib="1" name="AND Gate"/>
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<tool lib="1" name="OR Gate"/>
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</toolbar>
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<circuit name="main">
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<a name="circuit" val="main"/>
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<a name="clabel" val=""/>
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<a name="clabelup" val="east"/>
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<a name="clabelfont" val="SansSerif plain 12"/>
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<wire from="(180,160)" to="(340,160)"/>
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<wire from="(160,210)" to="(170,210)"/>
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<wire from="(180,150)" to="(180,160)"/>
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<wire from="(190,130)" to="(230,130)"/>
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<wire from="(260,140)" to="(260,250)"/>
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<wire from="(340,130)" to="(340,160)"/>
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<wire from="(260,140)" to="(300,140)"/>
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<wire from="(250,120)" to="(300,120)"/>
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<wire from="(170,150)" to="(170,210)"/>
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<wire from="(160,250)" to="(260,250)"/>
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<comp lib="0" loc="(160,210)" name="Clock"/>
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<comp lib="0" loc="(160,250)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="Rx"/>
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</comp>
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<comp lib="0" loc="(230,130)" name="Splitter">
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<a name="fanout" val="8"/>
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<a name="incoming" val="8"/>
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</comp>
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<comp lib="1" loc="(340,130)" name="NAND Gate">
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<a name="size" val="30"/>
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<a name="inputs" val="2"/>
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</comp>
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<comp lib="4" loc="(190,130)" name="Counter"/>
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</circuit>
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</project>
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