WIP routing mainboard
This commit is contained in:
parent
bf678289eb
commit
1ceee757e3
File diff suppressed because it is too large
Load Diff
3297
pat80-computer/hardware/schematics/pat80/pat80.kicad_pcb-bak
Normal file
3297
pat80-computer/hardware/schematics/pat80/pat80.kicad_pcb-bak
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,4 +1,4 @@
|
||||
update=sab 20 mar 2021 20:24:52 CET
|
||||
update=mer 24 mar 2021 21:27:02 CET
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
@ -39,8 +39,12 @@ MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.25
|
||||
TrackWidth2=0.25
|
||||
TrackWidth3=0.5
|
||||
ViaDiameter1=0.8
|
||||
ViaDrill1=0.4
|
||||
ViaDiameter2=1.5
|
||||
ViaDrill2=0.5
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
@ -67,7 +71,7 @@ OthersTextUpright=1
|
||||
SolderMaskClearance=0
|
||||
SolderMaskMinWidth=0
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=0
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
@ -233,7 +237,7 @@ Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=1
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
|
Loading…
Reference in New Issue
Block a user