Reset circuit

This commit is contained in:
Daniele Verducci su MatissePenguin 2021-03-15 20:12:23 +01:00
parent d2c3aa9bb2
commit 2a0750a06e
6 changed files with 968 additions and 322 deletions

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EESchema-LIBRARY Version 2.4 EESchema-LIBRARY Version 2.4
#encoding utf-8 #encoding utf-8
# #
# 74xx_74LS32
#
DEF 74xx_74LS32 U 0 40 Y Y 5 L N
F0 "U" 0 50 50 H V C CNN
F1 "74xx_74LS32" 0 -50 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
DIP?14*
$ENDFPLIST
DRAW
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ENDDRAW
ENDDEF
#
# CPU_Z80CPU # CPU_Z80CPU
# #
DEF CPU_Z80CPU U 0 40 Y Y 1 F N DEF CPU_Z80CPU U 0 40 Y Y 1 F N
@ -57,6 +130,41 @@ X D5 9 700 -1000 150 L 50 50 1 1 B
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
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ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
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X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Memory_EEPROM_28C256 # Memory_EEPROM_28C256
# #
DEF Memory_EEPROM_28C256 U 0 20 Y Y 1 F N DEF Memory_EEPROM_28C256 U 0 20 Y Y 1 F N
@ -101,4 +209,48 @@ X A1 9 -400 800 100 R 50 50 1 1 I
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# Switch_SW_Push
#
DEF Switch_SW_Push SW 0 40 N N 1 F N
F0 "SW" 50 100 50 H V L CNN
F1 "Switch_SW_Push" 0 -60 50 H V C CNN
F2 "" 0 200 50 H I C CNN
F3 "" 0 200 50 H I C CNN
DRAW
C -80 0 20 0 1 0 N
C 80 0 20 0 1 0 N
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P 2 0 1 0 100 50 -100 50 N
X 1 1 -200 0 100 R 50 50 0 1 P
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ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_VCC
#
DEF power_VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_VCC" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C 0 75 25 0 1 0 N
P 2 0 1 0 0 0 0 50 N
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ENDDRAW
ENDDEF
#
#End Library #End Library

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EESchema Schematic File Version 4 EESchema Schematic File Version 4
EELAYER 30 0 EELAYER 30 0
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$Descr A4 11693 8268 $Descr A3 16535 11693
encoding utf-8 encoding utf-8
Sheet 1 1 Sheet 1 1
Title "" Title ""
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Comment3 "" Comment3 ""
Comment4 "" Comment4 ""
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Pat80 Z80 home computer Pat80 Z80 home computer
Text Notes 8150 7650 0 50 ~ 0 Text Notes 13000 11050 0 50 ~ 0
2021-03-15 2021-03-15
$Comp $Comp
L CPU:Z80CPU U1
U 1 1 604F040E
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F 1 "Z80CPU" H 3150 4240 50 0000 C CNN
F 2 "" H 3150 3050 50 0001 C CNN
F 3 "www.zilog.com/manage_directlink.php?filepath=docs/z80/um0080" H 3150 3050 50 0001 C CNN
1 3150 2650
1 0 0 -1
$EndComp
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F 1 "256k (32k x 8) EEPROM" V 6805 556 50 0000 R CNN F 1 "256k (32k x 8) EEPROM" V 6855 856 50 0000 R CNN
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F 3 "http://ww1.microchip.com/downloads/en/DeviceDoc/doc0006.pdf" H 6850 1700 50 0001 C CNN F 3 "http://ww1.microchip.com/downloads/en/DeviceDoc/doc0006.pdf" H 6900 2000 50 0001 C CNN
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Text Label 5950 2750 3 50 ~ 0 Text Label 6000 3050 3 50 ~ 0
D0 D0
Text Label 6050 2750 3 50 ~ 0 Text Label 6100 3050 3 50 ~ 0
D1 D1
Text Label 6150 2750 3 50 ~ 0 Text Label 6200 3050 3 50 ~ 0
D2 D2
Text Label 6250 2750 3 50 ~ 0 Text Label 6300 3050 3 50 ~ 0
D3 D3
Text Label 6350 2750 3 50 ~ 0 Text Label 6400 3050 3 50 ~ 0
D4 D4
Text Label 6450 2750 3 50 ~ 0 Text Label 6500 3050 3 50 ~ 0
D5 D5
Text Label 6550 2750 3 50 ~ 0 Text Label 6600 3050 3 50 ~ 0
D6 D6
Text Label 6650 2750 3 50 ~ 0 Text Label 6700 3050 3 50 ~ 0
D7 D7
Text Label 3950 3150 0 50 ~ 0 Text Label 4000 3450 0 50 ~ 0
D0 D0
Text Label 3950 3250 0 50 ~ 0 Text Label 4000 3550 0 50 ~ 0
D1 D1
Text Label 3950 3350 0 50 ~ 0 Text Label 4000 3650 0 50 ~ 0
D2 D2
Text Label 3950 3450 0 50 ~ 0 Text Label 4000 3750 0 50 ~ 0
D3 D3
Text Label 3950 3550 0 50 ~ 0 Text Label 4000 3850 0 50 ~ 0
D4 D4
Text Label 3950 3650 0 50 ~ 0 Text Label 4000 3950 0 50 ~ 0
D5 D5
Text Label 3950 3750 0 50 ~ 0 Text Label 4000 4050 0 50 ~ 0
D6 D6
Text Label 3950 3850 0 50 ~ 0 Text Label 4000 4150 0 50 ~ 0
D7 D7
Entry Wire Line Entry Wire Line
4150 1450 4250 1550 4200 1750 4300 1850
$Comp
L Memory_EEPROM:28C256 U4
U 1 1 604FD5C5
P 6900 3550
F 0 "U4" V 6946 2406 50 0000 R CNN
F 1 "256k (32k x 8) SRAM" V 6855 2406 50 0000 R CNN
F 2 "" H 6900 3550 50 0001 C CNN
F 3 "http://ww1.microchip.com/downloads/en/DeviceDoc/doc0006.pdf" H 6900 3550 50 0001 C CNN
1 6900 3550
0 -1 -1 0
$EndComp
Wire Bus Line Wire Bus Line
6050 1100 8600 1100 5150 4150 5150 3350
$Comp
L power:GND #PWR?
U 1 1 60507104
P 8000 2000
F 0 "#PWR?" H 8000 1750 50 0001 C CNN
F 1 "GND" H 8005 1827 50 0000 C CNN
F 2 "" H 8000 2000 50 0001 C CNN
F 3 "" H 8000 2000 50 0001 C CNN
1 8000 2000
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6050737A
P 8000 3550
F 0 "#PWR?" H 8000 3300 50 0001 C CNN
F 1 "GND" H 8005 3377 50 0000 C CNN
F 2 "" H 8000 3550 50 0001 C CNN
F 3 "" H 8000 3550 50 0001 C CNN
1 8000 3550
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 605076F8
P 3200 4450
F 0 "#PWR?" H 3200 4200 50 0001 C CNN
F 1 "GND" H 3205 4277 50 0000 C CNN
F 2 "" H 3200 4450 50 0001 C CNN
F 3 "" H 3200 4450 50 0001 C CNN
1 3200 4450
1 0 0 -1
$EndComp
$Comp
L power:VCC #PWR?
U 1 1 60507B8E
P 3200 950
F 0 "#PWR?" H 3200 800 50 0001 C CNN
F 1 "VCC" H 3217 1123 50 0000 C CNN
F 2 "" H 3200 950 50 0001 C CNN
F 3 "" H 3200 950 50 0001 C CNN
1 3200 950
1 0 0 -1
$EndComp
$Comp
L power:VCC #PWR?
U 1 1 60507E3C
P 5800 2000
F 0 "#PWR?" H 5800 1850 50 0001 C CNN
F 1 "VCC" H 5817 2173 50 0000 C CNN
F 2 "" H 5800 2000 50 0001 C CNN
F 3 "" H 5800 2000 50 0001 C CNN
1 5800 2000
1 0 0 -1
$EndComp
$Comp
L power:VCC #PWR?
U 1 1 605080EF
P 5800 3550
F 0 "#PWR?" H 5800 3400 50 0001 C CNN
F 1 "VCC" H 5817 3723 50 0000 C CNN
F 2 "" H 5800 3550 50 0001 C CNN
F 3 "" H 5800 3550 50 0001 C CNN
1 5800 3550
1 0 0 -1
$EndComp
$Comp
L power:VCC #PWR?
U 1 1 60508CD5
P 2350 4050
F 0 "#PWR?" H 2350 3900 50 0001 C CNN
F 1 "VCC" H 2367 4223 50 0000 C CNN
F 2 "" H 2350 4050 50 0001 C CNN
F 3 "" H 2350 4050 50 0001 C CNN
1 2350 4050
1 0 0 -1
$EndComp
$Comp
L CPU:Z80CPU U1
U 1 1 604F040E
P 3200 2950
F 0 "U1" H 3200 4631 50 0000 C CNN
F 1 "Z80CPU" H 3200 4540 50 0000 C CNN
F 2 "" H 3200 3350 50 0001 C CNN
F 3 "www.zilog.com/manage_directlink.php?filepath=docs/z80/um0080" H 3200 3350 50 0001 C CNN
1 3200 2950
1 0 0 -1
$EndComp
Wire Wire Line
2500 2950 2350 2950
$Comp
L power:VCC #PWR?
U 1 1 6050EE1E
P 2350 2950
F 0 "#PWR?" H 2350 2800 50 0001 C CNN
F 1 "VCC" H 2367 3123 50 0000 C CNN
F 2 "" H 2350 2950 50 0001 C CNN
F 3 "" H 2350 2950 50 0001 C CNN
1 2350 2950
1 0 0 -1
$EndComp
$Comp
L 74xx:74LS32 U?
U 1 1 6051C888
P 1750 1750
F 0 "U?" H 1750 2075 50 0000 C CNN
F 1 "74LS32" H 1750 1984 50 0000 C CNN
F 2 "" H 1750 1750 50 0001 C CNN
F 3 "http://www.ti.com/lit/gpn/sn74LS32" H 1750 1750 50 0001 C CNN
1 1750 1750
1 0 0 -1
$EndComp
$Comp
L Switch:SW_Push SW1
U 1 1 60528DA4
P 1000 2050
F 0 "SW1" V 1000 2002 50 0000 R CNN
F 1 "SW_Push" V 955 2002 50 0001 R CNN
F 2 "" H 1000 2250 50 0001 C CNN
F 3 "" H 1000 2250 50 0001 C CNN
1 1000 2050
0 -1 -1 0
$EndComp
$Comp
L Device:C C?
U 1 1 6052B4C4
P 1350 2050
F 0 "C?" H 1465 2096 50 0000 L CNN
F 1 "10uF" H 1465 2005 50 0000 L CNN
F 2 "" H 1388 1900 50 0001 C CNN
F 3 "~" H 1350 2050 50 0001 C CNN
1 1350 2050
1 0 0 -1
$EndComp
Wire Wire Line
1350 1900 1350 1750
Wire Wire Line
1350 1750 1000 1750
Wire Wire Line
1000 1750 1000 1850
Wire Wire Line
1350 2200 1350 2250
$Comp
L power:VCC #PWR?
U 1 1 60530F78
P 1000 1200
F 0 "#PWR?" H 1000 1050 50 0001 C CNN
F 1 "VCC" H 1017 1373 50 0000 C CNN
F 2 "" H 1000 1200 50 0001 C CNN
F 3 "" H 1000 1200 50 0001 C CNN
1 1000 1200
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 605315B7
P 1000 2400
F 0 "#PWR?" H 1000 2150 50 0001 C CNN
F 1 "GND" H 1005 2227 50 0000 C CNN
F 2 "" H 1000 2400 50 0001 C CNN
F 3 "" H 1000 2400 50 0001 C CNN
1 1000 2400
1 0 0 -1
$EndComp
Wire Wire Line
1000 2250 1000 2400
Wire Wire Line
1000 2250 1350 2250
Connection ~ 1000 2250
Wire Wire Line
2050 1750 2500 1750
$Comp
L Device:C C?
U 1 1 6055A1F9
P 3600 950
F 0 "C?" V 3348 950 50 0000 C CNN
F 1 "100nF" V 3439 950 50 0000 C CNN
F 2 "" H 3638 800 50 0001 C CNN
F 3 "~" H 3600 950 50 0001 C CNN
1 3600 950
0 1 1 0
$EndComp
$Comp
L Device:C C?
U 1 1 6055A9DD
P 3600 1150
F 0 "C?" V 3348 1150 50 0000 C CNN
F 1 "56pF" V 3439 1150 50 0000 C CNN
F 2 "" H 3638 1000 50 0001 C CNN
F 3 "~" H 3600 1150 50 0001 C CNN
1 3600 1150
0 1 1 0
$EndComp
Wire Wire Line
3750 950 3750 1050
$Comp
L power:GND #PWR?
U 1 1 60567CC3
P 3850 1050
F 0 "#PWR?" H 3850 800 50 0001 C CNN
F 1 "GND" H 3855 877 50 0000 C CNN
F 2 "" H 3850 1050 50 0001 C CNN
F 3 "" H 3850 1050 50 0001 C CNN
1 3850 1050
1 0 0 -1
$EndComp
Wire Wire Line
3850 1050 3750 1050
Connection ~ 3750 1050
Wire Wire Line
3750 1050 3750 1150
Wire Wire Line
3200 950 3200 1050
Wire Wire Line
3450 1150 3450 1050
Wire Wire Line
3450 1050 3200 1050
Connection ~ 3450 1050
Wire Wire Line
3450 1050 3450 950
Connection ~ 3200 1050
Wire Wire Line
3200 1050 3200 1450
Text Notes 3350 1350 0 50 ~ 0
Smoothing caps
Text Notes 800 2800 0 50 ~ 0
Reset circuit with debouncing\nand power-on-reset
$Comp
L Device:R R?
U 1 1 60584118
P 1000 1500
F 0 "R?" H 1070 1546 50 0000 L CNN
F 1 "270k" H 1070 1455 50 0000 L CNN
F 2 "" V 930 1500 50 0001 C CNN
F 3 "~" H 1000 1500 50 0001 C CNN
1 1000 1500
1 0 0 -1
$EndComp
Wire Wire Line
1000 1650 1000 1750
Connection ~ 1000 1750
Wire Wire Line
1000 1350 1000 1200
Wire Wire Line
2500 4050 2350 4050
Text Notes 15450 11050 0 50 ~ 0
0.1 alpha
Wire Wire Line
1450 1650 1450 1750
Wire Wire Line
1350 1750 1450 1750
Wire Bus Line Wire Bus Line
6050 2650 8600 2650 6100 1400 8650 1400
Wire Bus Line Wire Bus Line
4250 3250 4250 4350 6100 2950 8650 2950
Wire Bus Line Wire Bus Line
4250 1550 4250 3050 4300 3550 4300 4650
Wire Bus Line Wire Bus Line
5100 2300 7250 2300 4300 1850 4300 3350
Wire Bus Line Wire Bus Line
5100 4050 7250 4050 5150 2600 7300 2600
Wire Bus Line
5150 4150 7300 4150
Connection ~ 1350 1750
Connection ~ 1450 1750
Wire Wire Line
1450 1750 1450 1850
$EndSCHEMATC $EndSCHEMATC

View File

@ -18,28 +18,6 @@ Pat80 Z80 home computer
Text Notes 8150 7650 0 50 ~ 0 Text Notes 8150 7650 0 50 ~ 0
2021-03-15 2021-03-15
$Comp $Comp
L CPU:Z80CPU U1
U 1 1 604F040E
P 3150 2650
F 0 "U1" H 3150 4331 50 0000 C CNN
F 1 "Z80CPU" H 3150 4240 50 0000 C CNN
F 2 "" H 3150 3050 50 0001 C CNN
F 3 "www.zilog.com/manage_directlink.php?filepath=docs/z80/um0080" H 3150 3050 50 0001 C CNN
1 3150 2650
1 0 0 -1
$EndComp
$Comp
L idleengineer:HM62256BLP-7 U2
U 1 1 604FA19C
P 6700 3350
F 0 "U2" V 6746 2506 50 0000 R CNN
F 1 "256k (32k x 8) SRAM" V 6655 2506 50 0000 R CNN
F 2 "DIP28" H 6700 3350 50 0001 C CIN
F 3 "" H 6700 3350 50 0001 C CNN
1 6700 3350
0 -1 -1 0
$EndComp
$Comp
L Memory_EEPROM:28C256 U3 L Memory_EEPROM:28C256 U3
U 1 1 604F6B81 U 1 1 604F6B81
P 6850 1700 P 6850 1700
@ -239,97 +217,95 @@ A13
Text Label 7350 2150 3 50 ~ 0 Text Label 7350 2150 3 50 ~ 0
A14 A14
Entry Wire Line Entry Wire Line
5950 3950 5850 4050 5950 3750 5850 3850
Entry Wire Line Entry Wire Line
6050 3950 5950 4050 6050 3750 5950 3850
Entry Wire Line Entry Wire Line
6150 3950 6050 4050 6150 3750 6050 3850
Entry Wire Line Entry Wire Line
6250 3950 6150 4050 6250 3750 6150 3850
Entry Wire Line Entry Wire Line
6350 3950 6250 4050 6350 3750 6250 3850
Entry Wire Line Entry Wire Line
6450 3950 6350 4050 6450 3750 6350 3850
Entry Wire Line Entry Wire Line
6550 3950 6450 4050 6550 3750 6450 3850
Entry Wire Line Entry Wire Line
6650 3950 6550 4050 6650 3750 6550 3850
Entry Wire Line Entry Wire Line
6750 3950 6650 4050 6750 3750 6650 3850
Entry Wire Line Entry Wire Line
6850 3950 6750 4050 6850 3750 6750 3850
Entry Wire Line Entry Wire Line
6950 3950 6850 4050 6950 3750 6850 3850
Entry Wire Line Entry Wire Line
7050 3950 6950 4050 7050 3750 6950 3850
Entry Wire Line Entry Wire Line
7150 3950 7050 4050 7150 3750 7050 3850
Entry Wire Line Entry Wire Line
7250 3950 7150 4050 7250 3750 7150 3850
Entry Wire Line Entry Wire Line
7350 3950 7250 4050 7350 3750 7250 3850
Wire Wire Line Wire Wire Line
5950 3950 5950 3850 5950 3750 5950 3650
Wire Wire Line Wire Wire Line
6050 3950 6050 3850 6050 3750 6050 3650
Wire Wire Line Wire Wire Line
6150 3950 6150 3850 6150 3750 6150 3650
Wire Wire Line Wire Wire Line
6250 3950 6250 3850 6250 3750 6250 3650
Wire Wire Line Wire Wire Line
6350 3950 6350 3850 6350 3750 6350 3650
Wire Wire Line Wire Wire Line
6450 3950 6450 3850 6450 3750 6450 3650
Wire Wire Line Wire Wire Line
6550 3950 6550 3850 6550 3750 6550 3650
Wire Wire Line Wire Wire Line
6650 3950 6650 3850 6650 3750 6650 3650
Wire Wire Line Wire Wire Line
6750 3950 6750 3850 6750 3750 6750 3650
Wire Wire Line Wire Wire Line
6850 3950 6850 3850 6850 3750 6850 3650
Wire Wire Line Wire Wire Line
6950 3950 6950 3850 6950 3750 6950 3650
Wire Wire Line Wire Wire Line
7050 3950 7050 3850 7050 3750 7050 3650
Wire Wire Line Wire Wire Line
7150 3950 7150 3850 7150 3750 7150 3650
Wire Wire Line Wire Wire Line
7250 3950 7250 3850 7250 3750 7250 3650
Wire Wire Line Wire Wire Line
7350 3950 7350 3850 7350 3750 7350 3650
Wire Bus Line
5100 4050 5100 3050
Connection ~ 5100 3050 Connection ~ 5100 3050
Text Label 5950 3900 3 50 ~ 0 Text Label 5950 3700 3 50 ~ 0
A0 A0
Text Label 6050 3900 3 50 ~ 0 Text Label 6050 3700 3 50 ~ 0
A1 A1
Text Label 6150 3900 3 50 ~ 0 Text Label 6150 3700 3 50 ~ 0
A2 A2
Text Label 6250 3900 3 50 ~ 0 Text Label 6250 3700 3 50 ~ 0
A3 A3
Text Label 6350 3900 3 50 ~ 0 Text Label 6350 3700 3 50 ~ 0
A4 A4
Text Label 6450 3900 3 50 ~ 0 Text Label 6450 3700 3 50 ~ 0
A5 A5
Text Label 6550 3900 3 50 ~ 0 Text Label 6550 3700 3 50 ~ 0
A6 A6
Text Label 6650 3900 3 50 ~ 0 Text Label 6650 3700 3 50 ~ 0
A7 A7
Text Label 6750 3900 3 50 ~ 0 Text Label 6750 3700 3 50 ~ 0
A8 A8
Text Label 6850 3900 3 50 ~ 0 Text Label 6850 3700 3 50 ~ 0
A9 A9
Text Label 6950 3900 3 50 ~ 0 Text Label 6950 3700 3 50 ~ 0
A10 A10
Text Label 7050 3900 3 50 ~ 0 Text Label 7050 3700 3 50 ~ 0
A11 A11
Text Label 7150 3900 3 50 ~ 0 Text Label 7150 3700 3 50 ~ 0
A12 A12
Text Label 7250 3900 3 50 ~ 0 Text Label 7250 3700 3 50 ~ 0
A13 A13
Text Label 7350 3900 3 50 ~ 0 Text Label 7350 3700 3 50 ~ 0
A14 A14
Entry Wire Line Entry Wire Line
4150 3150 4250 3250 4150 3150 4250 3250
@ -486,6 +462,270 @@ Text Label 3950 3850 0 50 ~ 0
D7 D7
Entry Wire Line Entry Wire Line
4150 1450 4250 1550 4150 1450 4250 1550
$Comp
L Memory_EEPROM:28C256 U4
U 1 1 604FD5C5
P 6850 3250
F 0 "U4" V 6896 2106 50 0000 R CNN
F 1 "256k (32k x 8) SRAM" V 6805 2106 50 0000 R CNN
F 2 "" H 6850 3250 50 0001 C CNN
F 3 "http://ww1.microchip.com/downloads/en/DeviceDoc/doc0006.pdf" H 6850 3250 50 0001 C CNN
1 6850 3250
0 -1 -1 0
$EndComp
Wire Bus Line
5100 3850 5100 3050
$Comp
L power:GND #PWR?
U 1 1 60507104
P 7950 1700
F 0 "#PWR?" H 7950 1450 50 0001 C CNN
F 1 "GND" H 7955 1527 50 0000 C CNN
F 2 "" H 7950 1700 50 0001 C CNN
F 3 "" H 7950 1700 50 0001 C CNN
1 7950 1700
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6050737A
P 7950 3250
F 0 "#PWR?" H 7950 3000 50 0001 C CNN
F 1 "GND" H 7955 3077 50 0000 C CNN
F 2 "" H 7950 3250 50 0001 C CNN
F 3 "" H 7950 3250 50 0001 C CNN
1 7950 3250
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 605076F8
P 3150 4150
F 0 "#PWR?" H 3150 3900 50 0001 C CNN
F 1 "GND" H 3155 3977 50 0000 C CNN
F 2 "" H 3150 4150 50 0001 C CNN
F 3 "" H 3150 4150 50 0001 C CNN
1 3150 4150
1 0 0 -1
$EndComp
$Comp
L power:VCC #PWR?
U 1 1 60507B8E
P 3150 650
F 0 "#PWR?" H 3150 500 50 0001 C CNN
F 1 "VCC" H 3167 823 50 0000 C CNN
F 2 "" H 3150 650 50 0001 C CNN
F 3 "" H 3150 650 50 0001 C CNN
1 3150 650
1 0 0 -1
$EndComp
$Comp
L power:VCC #PWR?
U 1 1 60507E3C
P 5750 1700
F 0 "#PWR?" H 5750 1550 50 0001 C CNN
F 1 "VCC" H 5767 1873 50 0000 C CNN
F 2 "" H 5750 1700 50 0001 C CNN
F 3 "" H 5750 1700 50 0001 C CNN
1 5750 1700
1 0 0 -1
$EndComp
$Comp
L power:VCC #PWR?
U 1 1 605080EF
P 5750 3250
F 0 "#PWR?" H 5750 3100 50 0001 C CNN
F 1 "VCC" H 5767 3423 50 0000 C CNN
F 2 "" H 5750 3250 50 0001 C CNN
F 3 "" H 5750 3250 50 0001 C CNN
1 5750 3250
1 0 0 -1
$EndComp
$Comp
L power:VCC #PWR?
U 1 1 60508CD5
P 2450 3750
F 0 "#PWR?" H 2450 3600 50 0001 C CNN
F 1 "VCC" H 2467 3923 50 0000 C CNN
F 2 "" H 2450 3750 50 0001 C CNN
F 3 "" H 2450 3750 50 0001 C CNN
1 2450 3750
1 0 0 -1
$EndComp
$Comp
L CPU:Z80CPU U1
U 1 1 604F040E
P 3150 2650
F 0 "U1" H 3150 4331 50 0000 C CNN
F 1 "Z80CPU" H 3150 4240 50 0000 C CNN
F 2 "" H 3150 3050 50 0001 C CNN
F 3 "www.zilog.com/manage_directlink.php?filepath=docs/z80/um0080" H 3150 3050 50 0001 C CNN
1 3150 2650
1 0 0 -1
$EndComp
Wire Wire Line
2450 2650 2300 2650
$Comp
L power:VCC #PWR?
U 1 1 6050EE1E
P 2300 2650
F 0 "#PWR?" H 2300 2500 50 0001 C CNN
F 1 "VCC" H 2317 2823 50 0000 C CNN
F 2 "" H 2300 2650 50 0001 C CNN
F 3 "" H 2300 2650 50 0001 C CNN
1 2300 2650
1 0 0 -1
$EndComp
$Comp
L 74xx:74LS32 U?
U 1 1 6051C888
P 1700 1450
F 0 "U?" H 1700 1775 50 0000 C CNN
F 1 "74LS32" H 1700 1684 50 0000 C CNN
F 2 "" H 1700 1450 50 0001 C CNN
F 3 "http://www.ti.com/lit/gpn/sn74LS32" H 1700 1450 50 0001 C CNN
1 1700 1450
1 0 0 -1
$EndComp
$Comp
L Switch:SW_Push SW1
U 1 1 60528DA4
P 950 1750
F 0 "SW1" V 950 1702 50 0000 R CNN
F 1 "SW_Push" V 905 1702 50 0001 R CNN
F 2 "" H 950 1950 50 0001 C CNN
F 3 "" H 950 1950 50 0001 C CNN
1 950 1750
0 -1 -1 0
$EndComp
$Comp
L Device:C C?
U 1 1 6052B4C4
P 1300 1750
F 0 "C?" H 1415 1796 50 0000 L CNN
F 1 "10uF" H 1415 1705 50 0000 L CNN
F 2 "" H 1338 1600 50 0001 C CNN
F 3 "~" H 1300 1750 50 0001 C CNN
1 1300 1750
1 0 0 -1
$EndComp
Wire Wire Line
1300 1600 1300 1450
Wire Wire Line
1300 1450 950 1450
Wire Wire Line
950 1450 950 1550
Wire Wire Line
1300 1900 1300 1950
$Comp
L power:VCC #PWR?
U 1 1 60530F78
P 950 900
F 0 "#PWR?" H 950 750 50 0001 C CNN
F 1 "VCC" H 967 1073 50 0000 C CNN
F 2 "" H 950 900 50 0001 C CNN
F 3 "" H 950 900 50 0001 C CNN
1 950 900
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 605315B7
P 950 2100
F 0 "#PWR?" H 950 1850 50 0001 C CNN
F 1 "GND" H 955 1927 50 0000 C CNN
F 2 "" H 950 2100 50 0001 C CNN
F 3 "" H 950 2100 50 0001 C CNN
1 950 2100
1 0 0 -1
$EndComp
Wire Wire Line
950 1950 950 2100
Wire Wire Line
950 1950 1300 1950
Connection ~ 950 1950
Wire Wire Line
1400 1350 1400 1450
Wire Wire Line
1300 1450 1400 1450
Connection ~ 1300 1450
Connection ~ 1400 1450
Wire Wire Line
1400 1450 1400 1550
Wire Wire Line
2000 1450 2450 1450
$Comp
L Device:C C?
U 1 1 6055A1F9
P 3550 650
F 0 "C?" V 3298 650 50 0000 C CNN
F 1 "100nF" V 3389 650 50 0000 C CNN
F 2 "" H 3588 500 50 0001 C CNN
F 3 "~" H 3550 650 50 0001 C CNN
1 3550 650
0 1 1 0
$EndComp
$Comp
L Device:C C?
U 1 1 6055A9DD
P 3550 850
F 0 "C?" V 3298 850 50 0000 C CNN
F 1 "56pF" V 3389 850 50 0000 C CNN
F 2 "" H 3588 700 50 0001 C CNN
F 3 "~" H 3550 850 50 0001 C CNN
1 3550 850
0 1 1 0
$EndComp
Wire Wire Line
3700 650 3700 750
$Comp
L power:GND #PWR?
U 1 1 60567CC3
P 3800 750
F 0 "#PWR?" H 3800 500 50 0001 C CNN
F 1 "GND" H 3805 577 50 0000 C CNN
F 2 "" H 3800 750 50 0001 C CNN
F 3 "" H 3800 750 50 0001 C CNN
1 3800 750
1 0 0 -1
$EndComp
Wire Wire Line
3800 750 3700 750
Connection ~ 3700 750
Wire Wire Line
3700 750 3700 850
Wire Wire Line
3150 650 3150 750
Wire Wire Line
3400 850 3400 750
Wire Wire Line
3400 750 3150 750
Connection ~ 3400 750
Wire Wire Line
3400 750 3400 650
Connection ~ 3150 750
Wire Wire Line
3150 750 3150 1150
Text Notes 3300 1050 0 50 ~ 0
Smoothing caps
Text Notes 750 2500 0 50 ~ 0
Reset circuit with debouncing\nand power-on-reset
$Comp
L Device:R R?
U 1 1 60584118
P 950 1200
F 0 "R?" H 1020 1246 50 0000 L CNN
F 1 "270k" H 1020 1155 50 0000 L CNN
F 2 "" V 880 1200 50 0001 C CNN
F 3 "~" H 950 1200 50 0001 C CNN
1 950 1200
1 0 0 -1
$EndComp
Wire Wire Line
950 1350 950 1450
Connection ~ 950 1450
Wire Wire Line
950 1050 950 900
Wire Bus Line Wire Bus Line
6050 1100 8600 1100 6050 1100 8600 1100
Wire Bus Line Wire Bus Line
@ -497,5 +737,5 @@ Wire Bus Line
Wire Bus Line Wire Bus Line
5100 2300 7250 2300 5100 2300 7250 2300
Wire Bus Line Wire Bus Line
5100 4050 7250 4050 5100 3850 7250 3850
$EndSCHEMATC $EndSCHEMATC

View File

@ -27,9 +27,8 @@ MON_ARG_HEX: DB " 0x",0
MON_HELP: DB 10,"Available commands:\nHELP prints this message\nDUMP [ADDR] shows memory content\nSET [ADDR] sets memory content\nZERO [ADDR] [ADDR] sets all bytes to 0 in the specified range\nLOAD\nRUN [ADDR] executes code starting from ADDR\nADB starts Assembly Deploy Bridge\nMEMTEST checks ram boundaries\nQUIT exits",0 MON_HELP: DB 10,"Available commands:\nHELP prints this message\nDUMP [ADDR] shows memory content\nSET [ADDR] sets memory content\nZERO [ADDR] [ADDR] sets all bytes to 0 in the specified range\nLOAD\nRUN [ADDR] executes code starting from ADDR\nADB starts Assembly Deploy Bridge\nMEMTEST checks ram boundaries\nQUIT exits",0
MON_MSG_ADB: DB 10,"Waiting for data.",0 MON_MSG_ADB: DB 10,"Waiting for data.",0
MON_ERR_SYNTAX: DB " Syntax error",0 MON_ERR_SYNTAX: DB " Syntax error",0
MON_RAMTEST_INTRO: DB " Checking memory... ",0 ; MON_RAMTEST_INTRO: DB " Checking memory... ",0
MON_RAMTEST_RAMSTART: DB " Ram starts at 0x",0 ; MON_RAMTEST_RAMSTART: DB " Ram starts at 0x",0
;MON_ADB_TIMEOUT: EQU 0xFF // Number of cycles after an ADB binary transfer is considered completed
MON_DUMP_BYTES_LINES: EQU 8 MON_DUMP_BYTES_LINES: EQU 8
MON_DUMP_BYTES_PER_LINE: EQU 8 MON_DUMP_BYTES_PER_LINE: EQU 8
@ -70,9 +69,9 @@ Monitor_main:
ld hl, MON_COMMAND_ADB ld hl, MON_COMMAND_ADB
cp (hl) cp (hl)
jp z, monitor_adb jp z, monitor_adb
ld hl, MON_COMMAND_MEMTEST ; ld hl, MON_COMMAND_MEMTEST
cp (hl) ; cp (hl)
jp z, monitor_memtest ; jp z, monitor_memtest
ld hl, MON_COMMAND_QUIT ld hl, MON_COMMAND_QUIT
cp (hl) cp (hl)
jp z, monitor_quit jp z, monitor_quit