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WIP Mainboard schematics: added CPU, RAM, ROM, Addr and data bus.

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TODO: Fix external dependency
This commit is contained in:
Daniele Verducci (ZenPenguin) 2021-03-15 08:58:44 +01:00
parent faef987494
commit 6890e352c1
6 changed files with 1187 additions and 0 deletions
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148
pat80-computer/hardware/schematics/pat80/pat80-cache.lib Normal file
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# CPU_Z80CPU
#
DEF CPU_Z80CPU U 0 40 Y Y 1 F N
F0 "U" -550 1400 50 H V L CNN
F1 "CPU_Z80CPU" 250 1400 50 H V L CNN
F2 "" 0 400 50 H I C CNN
F3 "" 0 400 50 H I C CNN
$FPLIST
DIP*
PDIP*
$ENDFPLIST
DRAW
S -550 1350 550 -1350 0 1 10 f
X A11 1 700 100 150 L 50 50 1 1 O
X D6 10 700 -1100 150 L 50 50 1 1 B
X VCC 11 0 1500 150 D 50 50 1 1 W
X D2 12 700 -700 150 L 50 50 1 1 B
X D7 13 700 -1200 150 L 50 50 1 1 B
X D0 14 700 -500 150 L 50 50 1 1 B
X D1 15 700 -600 150 L 50 50 1 1 B
X ~INT~ 16 -700 500 150 R 50 50 1 1 I
X ~NMI~ 17 -700 600 150 R 50 50 1 1 I
X ~HALT~ 18 -700 -100 150 R 50 50 1 1 O
X ~MREQ~ 19 -700 -700 150 R 50 50 1 1 O
X A12 2 700 0 150 L 50 50 1 1 O
X ~IORQ~ 20 -700 -800 150 R 50 50 1 1 O
X ~RD~ 21 -700 -500 150 R 50 50 1 1 O
X ~WR~ 22 -700 -600 150 R 50 50 1 1 O
X ~BUSACK~ 23 -700 -1200 150 R 50 50 1 1 O
X ~WAIT~ 24 -700 0 150 R 50 50 1 1 I
X ~BUSRQ~ 25 -700 -1100 150 R 50 50 1 1 I
X ~RESET~ 26 -700 1200 150 R 50 50 1 1 I
X ~M1~ 27 -700 200 150 R 50 50 1 1 O
X ~RFSH~ 28 -700 100 150 R 50 50 1 1 O
X GND 29 0 -1500 150 U 50 50 1 1 W
X A13 3 700 -100 150 L 50 50 1 1 O
X A0 30 700 1200 150 L 50 50 1 1 O
X A1 31 700 1100 150 L 50 50 1 1 O
X A2 32 700 1000 150 L 50 50 1 1 O
X A3 33 700 900 150 L 50 50 1 1 O
X A4 34 700 800 150 L 50 50 1 1 O
X A5 35 700 700 150 L 50 50 1 1 O
X A6 36 700 600 150 L 50 50 1 1 O
X A7 37 700 500 150 L 50 50 1 1 O
X A8 38 700 400 150 L 50 50 1 1 O
X A9 39 700 300 150 L 50 50 1 1 O
X A14 4 700 -200 150 L 50 50 1 1 O
X A10 40 700 200 150 L 50 50 1 1 O
X A15 5 700 -300 150 L 50 50 1 1 O
X ~CLK~ 6 -700 900 150 R 50 50 1 1 I C
X D4 7 700 -900 150 L 50 50 1 1 B
X D3 8 700 -800 150 L 50 50 1 1 B
X D5 9 700 -1000 150 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# Memory_EEPROM_28C256
#
DEF Memory_EEPROM_28C256 U 0 20 Y Y 1 F N
F0 "U" -300 1050 50 H V C CNN
F1 "Memory_EEPROM_28C256" 100 -1050 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
DIP*W15.24mm*
SOIC*7.5x17.9mm*P1.27mm*
$ENDFPLIST
DRAW
S -300 1000 300 -1000 1 1 10 f
X A14 1 -400 -500 100 R 50 50 1 1 I
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X D1 12 400 800 100 L 50 50 1 1 T
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X ~OE 22 -400 -800 100 R 50 50 1 1 I
X A11 23 -400 -200 100 R 50 50 1 1 I
X A9 24 -400 0 100 R 50 50 1 1 I
X A8 25 -400 100 100 R 50 50 1 1 I
X A13 26 -400 -400 100 R 50 50 1 1 I
X ~WE 27 -400 -700 100 R 50 50 1 1 I
X VCC 28 0 1100 100 D 50 50 1 1 W
X A7 3 -400 200 100 R 50 50 1 1 I
X A6 4 -400 300 100 R 50 50 1 1 I
X A5 5 -400 400 100 R 50 50 1 1 I
X A4 6 -400 500 100 R 50 50 1 1 I
X A3 7 -400 600 100 R 50 50 1 1 I
X A2 8 -400 700 100 R 50 50 1 1 I
X A1 9 -400 800 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# idleengineer_HM62256BLP-7
#
DEF idleengineer_HM62256BLP-7 U 0 40 Y Y 1 F N
F0 "U" -300 900 50 H V C CNN
F1 "idleengineer_HM62256BLP-7" 400 -800 50 H V C CNN
F2 "DIP28" 0 0 50 H I C CIN
F3 "" 0 0 50 H I C CNN
ALIAS HM62256BLP-7SL
$FPLIST
DIP28*
$ENDFPLIST
DRAW
S -400 850 400 -750 0 1 10 f
X GND 14 0 -800 50 U 40 40 0 0 W N
X VCC 28 0 900 50 D 40 40 0 0 W N
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X A0 10 -500 750 100 R 40 40 1 1 I
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X D3 15 500 450 100 L 40 40 1 1 T
X D4 16 500 350 100 L 40 40 1 1 T
X D5 17 500 250 100 L 40 40 1 1 T
X D6 18 500 150 100 L 40 40 1 1 T
X D7 19 500 50 100 L 40 40 1 1 T
X A12 2 -500 -450 100 R 40 40 1 1 I
X ~CS 20 500 -350 100 L 40 40 1 1 I
X A10 21 -500 -250 100 R 40 40 1 1 I
X ~OE 22 500 -100 100 L 40 40 1 1 I
X A11 23 -500 -350 100 R 40 40 1 1 I
X A9 24 -500 -150 100 R 40 40 1 1 I
X A8 25 -500 -50 100 R 40 40 1 1 I
X A13 26 -500 -550 100 R 40 40 1 1 I
X ~WE 27 500 -200 100 L 40 40 1 1 I
X A7 3 -500 50 100 R 40 40 1 1 I
X A6 4 -500 150 100 R 40 40 1 1 I
X A5 5 -500 250 100 R 40 40 1 1 I
X A4 6 -500 350 100 R 40 40 1 1 I
X A3 7 -500 450 100 R 40 40 1 1 I
X A2 8 -500 550 100 R 40 40 1 1 I
X A1 9 -500 650 100 R 40 40 1 1 I
ENDDRAW
ENDDEF
#
#End Library

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pat80-computer/hardware/schematics/pat80/pat80.kicad_pcb Normal file
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(kicad_pcb (version 4) (host kicad "dummy file") )

33
pat80-computer/hardware/schematics/pat80/pat80.pro Normal file
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update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]

501
pat80-computer/hardware/schematics/pat80/pat80.sch Normal file
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EESchema Schematic File Version 4
EELAYER 30 0
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$Comp
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$EndComp
$Comp
L Memory_EEPROM:28C256 U3
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EESchema Schematic File Version 4
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$Comp
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0 -1 -1 0
$EndComp
$Comp
L Memory_EEPROM:28C256 U3
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1 6850 1700
0 -1 -1 0
$EndComp
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7350 2100 7350 2200
Wire Bus Line
5100 3050 5100 2300
Text Label 3950 1450 0 50 ~ 0
A0
Text Label 3950 1550 0 50 ~ 0
A1
Text Label 3950 1650 0 50 ~ 0
A2
Text Label 3950 1750 0 50 ~ 0
A3
Text Label 3950 1850 0 50 ~ 0
A4
Text Label 3950 1950 0 50 ~ 0
A5
Text Label 3950 2050 0 50 ~ 0
A6
Text Label 3950 2150 0 50 ~ 0
A7
Text Label 3950 2250 0 50 ~ 0
A8
Text Label 3950 2350 0 50 ~ 0
A9
Text Label 3950 2450 0 50 ~ 0
A10
Text Label 3950 2550 0 50 ~ 0
A11
Text Label 3950 2650 0 50 ~ 0
A12
Text Label 3950 2750 0 50 ~ 0
A13
Text Label 3950 2850 0 50 ~ 0
A14
Text Label 3950 2950 0 50 ~ 0
A15
Text Label 5950 2150 3 50 ~ 0
A0
Text Label 6050 2150 3 50 ~ 0
A1
Text Label 6150 2150 3 50 ~ 0
A2
Text Label 6250 2150 3 50 ~ 0
A3
Text Label 6350 2150 3 50 ~ 0
A4
Text Label 6450 2150 3 50 ~ 0
A5
Text Label 6550 2150 3 50 ~ 0
A6
Text Label 6650 2150 3 50 ~ 0
A7
Text Label 6750 2150 3 50 ~ 0
A8
Text Label 6850 2150 3 50 ~ 0
A9
Text Label 6950 2150 3 50 ~ 0
A10
Text Label 7050 2150 3 50 ~ 0
A11
Text Label 7150 2150 3 50 ~ 0
A12
Text Label 7250 2150 3 50 ~ 0
A13
Text Label 7350 2150 3 50 ~ 0
A14
Entry Wire Line
5950 3950 5850 4050
Entry Wire Line
6050 3950 5950 4050
Entry Wire Line
6150 3950 6050 4050
Entry Wire Line
6250 3950 6150 4050
Entry Wire Line
6350 3950 6250 4050
Entry Wire Line
6450 3950 6350 4050
Entry Wire Line
6550 3950 6450 4050
Entry Wire Line
6650 3950 6550 4050
Entry Wire Line
6750 3950 6650 4050
Entry Wire Line
6850 3950 6750 4050
Entry Wire Line
6950 3950 6850 4050
Entry Wire Line
7050 3950 6950 4050
Entry Wire Line
7150 3950 7050 4050
Entry Wire Line
7250 3950 7150 4050
Entry Wire Line
7350 3950 7250 4050
Wire Wire Line
5950 3950 5950 3850
Wire Wire Line
6050 3950 6050 3850
Wire Wire Line
6150 3950 6150 3850
Wire Wire Line
6250 3950 6250 3850
Wire Wire Line
6350 3950 6350 3850
Wire Wire Line
6450 3950 6450 3850
Wire Wire Line
6550 3950 6550 3850
Wire Wire Line
6650 3950 6650 3850
Wire Wire Line
6750 3950 6750 3850
Wire Wire Line
6850 3950 6850 3850
Wire Wire Line
6950 3950 6950 3850
Wire Wire Line
7050 3950 7050 3850
Wire Wire Line
7150 3950 7150 3850
Wire Wire Line
7250 3950 7250 3850
Wire Wire Line
7350 3950 7350 3850
Wire Bus Line
5100 4050 5100 3050
Connection ~ 5100 3050
Text Label 5950 3900 3 50 ~ 0
A0
Text Label 6050 3900 3 50 ~ 0
A1
Text Label 6150 3900 3 50 ~ 0
A2
Text Label 6250 3900 3 50 ~ 0
A3
Text Label 6350 3900 3 50 ~ 0
A4
Text Label 6450 3900 3 50 ~ 0
A5
Text Label 6550 3900 3 50 ~ 0
A6
Text Label 6650 3900 3 50 ~ 0
A7
Text Label 6750 3900 3 50 ~ 0
A8
Text Label 6850 3900 3 50 ~ 0
A9
Text Label 6950 3900 3 50 ~ 0
A10
Text Label 7050 3900 3 50 ~ 0
A11
Text Label 7150 3900 3 50 ~ 0
A12
Text Label 7250 3900 3 50 ~ 0
A13
Text Label 7350 3900 3 50 ~ 0
A14
Entry Wire Line
4150 3150 4250 3250
Entry Wire Line
4150 3150 4250 3250
Entry Wire Line
4150 3250 4250 3350
Entry Wire Line
4150 3350 4250 3450
Entry Wire Line
4150 3450 4250 3550
Entry Wire Line
4150 3550 4250 3650
Entry Wire Line
4150 3650 4250 3750
Entry Wire Line
4150 3750 4250 3850
Entry Wire Line
4150 3850 4250 3950
Wire Wire Line
3850 3150 4150 3150
Wire Wire Line
3850 3250 4150 3250
Wire Wire Line
3850 3350 4150 3350
Wire Wire Line
3850 3450 4150 3450
Wire Wire Line
3850 3550 4150 3550
Wire Wire Line
3850 3650 4150 3650
Wire Wire Line
3850 3750 4150 3750
Wire Wire Line
3850 3850 4150 3850
Wire Bus Line
4250 4350 8600 4350
Entry Wire Line
5950 2750 6050 2650
Entry Wire Line
6150 2650 6050 2750
Entry Wire Line
6250 2650 6150 2750
Entry Wire Line
6350 2650 6250 2750
Entry Wire Line
6450 2650 6350 2750
Entry Wire Line
6550 2650 6450 2750
Entry Wire Line
6650 2650 6550 2750
Entry Wire Line
6750 2650 6650 2750
Wire Wire Line
5950 2850 5950 2750
Wire Wire Line
6050 2850 6050 2750
Wire Wire Line
6150 2850 6150 2750
Wire Wire Line
6250 2850 6250 2750
Wire Wire Line
6350 2850 6350 2750
Wire Wire Line
6450 2850 6450 2750
Wire Wire Line
6550 2850 6550 2750
Wire Wire Line
6650 2850 6650 2750
Wire Bus Line
8600 2650 8600 4350
Entry Wire Line
6050 1100 5950 1200
Entry Wire Line
6150 1100 6050 1200
Entry Wire Line
6250 1100 6150 1200
Entry Wire Line
6350 1100 6250 1200
Entry Wire Line
6450 1100 6350 1200
Entry Wire Line
6550 1100 6450 1200
Entry Wire Line
6650 1100 6550 1200
Entry Wire Line
6750 1100 6650 1200
Wire Wire Line
5950 1300 5950 1200
Wire Wire Line
6050 1300 6050 1200
Wire Wire Line
6150 1300 6150 1200
Wire Wire Line
6250 1300 6250 1200
Wire Wire Line
6350 1300 6350 1200
Wire Wire Line
6450 1300 6450 1200
Wire Wire Line
6550 1300 6550 1200
Wire Wire Line
6650 1300 6650 1200
Wire Bus Line
8600 1100 8600 2650
Connection ~ 8600 2650
Text Label 5950 1200 3 50 ~ 0
D0
Text Label 6050 1200 3 50 ~ 0
D1
Text Label 6150 1200 3 50 ~ 0
D2
Text Label 6250 1200 3 50 ~ 0
D3
Text Label 6350 1200 3 50 ~ 0
D4
Text Label 6450 1200 3 50 ~ 0
D5
Text Label 6550 1200 3 50 ~ 0
D6
Text Label 6650 1200 3 50 ~ 0
D7
Text Label 5950 2750 3 50 ~ 0
D0
Text Label 6050 2750 3 50 ~ 0
D1
Text Label 6150 2750 3 50 ~ 0
D2
Text Label 6250 2750 3 50 ~ 0
D3
Text Label 6350 2750 3 50 ~ 0
D4
Text Label 6450 2750 3 50 ~ 0
D5
Text Label 6550 2750 3 50 ~ 0
D6
Text Label 6650 2750 3 50 ~ 0
D7
Text Label 3950 3150 0 50 ~ 0
D0
Text Label 3950 3250 0 50 ~ 0
D1
Text Label 3950 3350 0 50 ~ 0
D2
Text Label 3950 3450 0 50 ~ 0
D3
Text Label 3950 3550 0 50 ~ 0
D4
Text Label 3950 3650 0 50 ~ 0
D5
Text Label 3950 3750 0 50 ~ 0
D6
Text Label 3950 3850 0 50 ~ 0
D7
Wire Bus Line
4250 3250 4250 4350
Wire Bus Line
6050 2650 8600 2650
Wire Bus Line
6050 1100 8600 1100
Wire Bus Line
5100 2300 7250 2300
Wire Bus Line
5100 4050 7250 4050
Wire Bus Line
4250 1450 4250 3050
$EndSCHEMATC

3
pat80-computer/hardware/schematics/pat80/sym-lib-table Normal file
View File

@ -0,0 +1,3 @@
(sym_lib_table
(lib (name idleengineer)(type Legacy)(uri /home/danieleverducci/kicad-libs/idleengineer/symbols/Memory_RAM.lib)(options "")(descr ""))
)