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Fixed halved number of sync pulses

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Daniele Verducci su MatissePenguin 2021-01-17 17:09:13 +01:00
parent 8b2063c6bc
commit b3269125ac
1 changed files with 19 additions and 26 deletions
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45
pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm
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@ -19,12 +19,12 @@
; ;
; STATUS TABLE: ; STATUS TABLE:
; R25 (STATUS): Current status (what the interrupt should do when fired): ; R25 (STATUS): Current status (what the interrupt should do when fired):
; 0, 1, 2, 3, 4 = long sync ; 0-9 = long sync
; 5, 6, 7, 8, 9 = short sync ; 10-19 = short sync
; 10 = draw lines (draw 304 lines complete with line sync and back porch, then start short ; 20 = draw lines (draw 304 lines complete with line sync and back porch, then start short
; sync: sync pin low and next interrupt after 2uS) ; sync: sync pin low and next interrupt after 2uS)
; 11, 12, 13, 14, 15, 16 = short sync ; 21-32 = short sync
; 17-255 = invalid state or screen draw finished: set to 0 and restart from first long sync start ; 33-255 = invalid state or screen draw finished: set to 0 and restart from first long sync start
.include "m1284def.inc" .include "m1284def.inc"
@ -35,8 +35,8 @@
; define constant ; define constant
.equ SYNC_PIN = PC0 ; Sync pin (pin 22) .equ SYNC_PIN = PC0 ; Sync pin (pin 22)
.equ DEBUG_PIN = PC1 ; DEBUG: Single vertical sync pulse to trigger oscilloscope (pin 23) .equ DEBUG_PIN = PC1 ; DEBUG: Single vertical sync pulse to trigger oscilloscope (pin 23)
.equ TIMER_DELAY_30US = 65535 - 704 ; 719 cycles @ 24Mhz .equ TIMER_DELAY_30US = 65535 - 690 ; 719 cycles @ 24Mhz (minus overhead)
.equ TIMER_DELAY_2US = 65535 - 47 ; 48 cycles @ 24Mhz .equ TIMER_DELAY_2US = 65535 - 17 ; 48 cycles @ 24Mhz (minus overhead)
; memory ; memory
.equ FRAMEBUFFER = 0x100 .equ FRAMEBUFFER = 0x100
@ -113,23 +113,21 @@ on_tim1_ovf:
; called by timer 1 two times per line (every 32 uS) during hsync, unless drawing picture. ; called by timer 1 two times per line (every 32 uS) during hsync, unless drawing picture.
inc STATUS
; if STATUS >= 17 then STATUS=0 ; if STATUS >= 33 then STATUS=0
cpi STATUS, 17 cpi STATUS, 33
brlo switch_status brlo switch_status
clr STATUS clr STATUS
; check status and decide what to do ; check status and decide what to do
switch_status: switch_status:
cpi STATUS, 5 cpi STATUS, 10
brlo long_sync ; 0-4: long sync brlo long_sync ; 0-9: long sync
cpi STATUS, 10 ; 5-9: short sync cpi STATUS, 20
breq draw_picture ; 10: draw picture breq draw_picture ; 20: draw picture
jmp short_sync ; 11-16: short_sync jmp short_sync ; 10-19 or 21-32: short_sync
; reti is at end of all previous jumps ; reti is at end of all previous jumps
draw_picture: draw_picture:
; increment status
inc STATUS
; set X register to framebuffer start 0x0100 ; set X register to framebuffer start 0x0100
; (set it a byte before, because it will be incremented at first) ; (set it a byte before, because it will be incremented at first)
clr r27 clr r27
@ -219,18 +217,14 @@ draw_picture:
; debug ; debug
; immediately start first end-screen short sync (set timer in 0uS): ; immediately start first end-screen short sync:
;ldi r27, 0xFF inc STATUS
;ldi r26, 0xFF jmp short_sync
;sts TCNT1H,r27 ; reti is in short_sync
;sts TCNT1L,r26
reti
; end draw_picture ; end draw_picture
long_sync: long_sync:
; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz) ; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz)
inc STATUS ; increment status counter
sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
jmp long_sync_end jmp long_sync_end
@ -256,7 +250,6 @@ long_sync:
short_sync: short_sync:
; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz) ; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz)
inc STATUS ; increment status counter
sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
jmp short_sync_end jmp short_sync_end