Merge branch 'master' into monitor-interrupt

pat80-computer/software/z80-assembly/os/main.asm

@@ -117,3 +117,9 @@ Sysinit:
 	mloop:
 		; Main loop: do nothing.
 		jp mloop
+
+    ; DEBUG: Echo chars
+    ; loop:
+    ;     call Term_readc
+    ;     call Term_printc
+    ;     jp loop

pat80-io-devices/composite-pal-adapter/software/avr-assembly/Makefile

@@ -0,0 +1,5 @@
+pal-adapter:
+	@echo "Building pal adapter rom..."
+	@avra main.asm
+	@echo "Writing to ATMEGA1284..."
+	@minipro -w main.hex -p ATMEGA1284

pat80-io-devices/composite-pal-adapter/software/avr-assembly/README.md

@@ -0,0 +1,13 @@
+# Atmega Microcontroller
+## Build ASM code
+`avra filename.asm` (generates *filename.hex*)
+
+## Flash
+### Rom
+`minipro -w filename.hex -p ATMEGA1284`
+
+### Fuses
+Read fuses: `minipro -r -c config -p ATMEGA1284` (`-r -c config` means read configuration (fuses))
+Fuses must be written all together, so read the current values, edit the generated file and write it.
+The meaning of every bis is in the conf file.
+Write fuses: `minipro -w fuses.conf -c config -p ATMEGA1284`

pat80-io-devices/composite-pal-adapter/software/avr-assembly/atmega1284definition.asm

@@ -0,0 +1,276 @@
+; ***** I/O REGISTER DEFINITIONS *****************************************
+; NOTE:
+; Definitions marked "MEMORY MAPPED"are extended I/O ports
+; and cannot be used with IN/OUT instructions
+.equ	UDR1	= 0xce	; MEMORY MAPPED
+.equ	UBRR1L	= 0xcc	; MEMORY MAPPED
+.equ	UBRR1H	= 0xcd	; MEMORY MAPPED
+.equ	UCSR1C	= 0xca	; MEMORY MAPPED
+.equ	UCSR1B	= 0xc9	; MEMORY MAPPED
+.equ	UCSR1A	= 0xc8	; MEMORY MAPPED
+.equ	UDR0	= 0xc6	; MEMORY MAPPED
+.equ	UBRR0L	= 0xc4	; MEMORY MAPPED
+.equ	UBRR0H	= 0xc5	; MEMORY MAPPED
+.equ	UCSR0C	= 0xc2	; MEMORY MAPPED
+.equ	UCSR0B	= 0xc1	; MEMORY MAPPED
+.equ	UCSR0A	= 0xc0	; MEMORY MAPPED
+.equ	TWAMR	= 0xbd	; MEMORY MAPPED
+.equ	TWCR	= 0xbc	; MEMORY MAPPED
+.equ	TWDR	= 0xbb	; MEMORY MAPPED
+.equ	TWAR	= 0xba	; MEMORY MAPPED
+.equ	TWSR	= 0xb9	; MEMORY MAPPED
+.equ	TWBR	= 0xb8	; MEMORY MAPPED
+.equ	ASSR	= 0xb6	; MEMORY MAPPED
+.equ	OCR2B	= 0xb4	; MEMORY MAPPED
+.equ	OCR2A	= 0xb3	; MEMORY MAPPED
+.equ	TCNT2	= 0xb2	; MEMORY MAPPED
+.equ	TCCR2B	= 0xb1	; MEMORY MAPPED
+.equ	TCCR2A	= 0xb0	; MEMORY MAPPED
+.equ	OCR3BL	= 0x9a	; MEMORY MAPPED
+.equ	OCR3BH	= 0x9b	; MEMORY MAPPED
+.equ	OCR3AL	= 0x98	; MEMORY MAPPED
+.equ	OCR3AH	= 0x99	; MEMORY MAPPED
+.equ	ICR3L	= 0x96	; MEMORY MAPPED
+.equ	ICR3H	= 0x97	; MEMORY MAPPED
+.equ	TCNT3L	= 0x94	; MEMORY MAPPED
+.equ	TCNT3H	= 0x95	; MEMORY MAPPED
+.equ	TCCR3C	= 0x92	; MEMORY MAPPED
+.equ	TCCR3B	= 0x91	; MEMORY MAPPED
+.equ	TCCR3A	= 0x90	; MEMORY MAPPED
+.equ	OCR1BL	= 0x8a	; MEMORY MAPPED
+.equ	OCR1BH	= 0x8b	; MEMORY MAPPED
+.equ	OCR1AL	= 0x88	; MEMORY MAPPED
+.equ	OCR1AH	= 0x89	; MEMORY MAPPED
+.equ	ICR1L	= 0x86	; MEMORY MAPPED
+.equ	ICR1H	= 0x87	; MEMORY MAPPED
+.equ	TCNT1L	= 0x84	; MEMORY MAPPED
+.equ	TCNT1H	= 0x85	; MEMORY MAPPED
+.equ	TCCR1C	= 0x82	; MEMORY MAPPED
+.equ	TCCR1B	= 0x81	; MEMORY MAPPED
+.equ	TCCR1A	= 0x80	; MEMORY MAPPED
+.equ	DIDR1	= 0x7f	; MEMORY MAPPED
+.equ	DIDR0	= 0x7e	; MEMORY MAPPED
+.equ	ADMUX	= 0x7c	; MEMORY MAPPED
+.equ	ADCSRB	= 0x7b	; MEMORY MAPPED
+.equ	ADCSRA	= 0x7a	; MEMORY MAPPED
+.equ	ADCH	= 0x79	; MEMORY MAPPED
+.equ	ADCL	= 0x78	; MEMORY MAPPED
+.equ	PCMSK3	= 0x73	; MEMORY MAPPED
+.equ	TIMSK3	= 0x71	; MEMORY MAPPED
+.equ	TIMSK2	= 0x70	; MEMORY MAPPED
+.equ	TIMSK1	= 0x6f	; MEMORY MAPPED
+.equ	TIMSK0	= 0x6e	; MEMORY MAPPED
+.equ	PCMSK2	= 0x6d	; MEMORY MAPPED
+.equ	PCMSK1	= 0x6c	; MEMORY MAPPED
+.equ	PCMSK0	= 0x6b	; MEMORY MAPPED
+.equ	EICRA	= 0x69	; MEMORY MAPPED
+.equ	PCICR	= 0x68	; MEMORY MAPPED
+.equ	OSCCAL	= 0x66	; MEMORY MAPPED
+.equ	PRR1	= 0x65	; MEMORY MAPPED
+.equ	PRR0	= 0x64	; MEMORY MAPPED
+.equ	CLKPR	= 0x61	; MEMORY MAPPED
+.equ	WDTCSR	= 0x60	; MEMORY MAPPED
+.equ	SREG	= 0x3f
+.equ	SPL	= 0x3d
+.equ	SPH	= 0x3e
+.equ	RAMPZ	= 0x3b
+.equ	SPMCSR	= 0x37
+.equ	MCUCR	= 0x35
+.equ	MCUSR	= 0x34
+.equ	SMCR	= 0x33
+.equ	OCDR	= 0x31
+.equ	ACSR	= 0x30
+.equ	SPDR	= 0x2e
+.equ	SPSR	= 0x2d
+.equ	SPCR	= 0x2c
+.equ	GPIOR2	= 0x2b
+.equ	GPIOR1	= 0x2a
+.equ	OCR0B	= 0x28
+.equ	OCR0A	= 0x27
+.equ	TCNT0	= 0x26
+.equ	TCCR0B	= 0x25
+.equ	TCCR0A	= 0x24
+.equ	GTCCR	= 0x23
+.equ	EEARH	= 0x22
+.equ	EEARL	= 0x21
+.equ	EEDR	= 0x20
+.equ	EECR	= 0x1f
+.equ	GPIOR0	= 0x1e
+.equ	EIMSK	= 0x1d
+.equ	EIFR	= 0x1c
+.equ	PCIFR	= 0x1b
+.equ	TIFR3	= 0x18
+.equ	TIFR2	= 0x17
+.equ	TIFR1	= 0x16
+.equ	TIFR0	= 0x15
+.equ	PORTD	= 0x0b
+.equ	DDRD	= 0x0a
+.equ	PIND	= 0x09
+.equ	PORTC	= 0x08
+.equ	DDRC	= 0x07
+.equ	PINC	= 0x06
+.equ	PORTB	= 0x05
+.equ	DDRB	= 0x04
+.equ	PINB	= 0x03
+.equ	PORTA	= 0x02
+.equ	DDRA	= 0x01
+.equ	PINA	= 0x00
+
+; ***** PORTA ************************
+; PORTA - Port A Data Register
+.equ	PORTA0	= 0	; Port A Data Register bit 0
+.equ	PA0	= 0	; For compatibility
+.equ	PORTA1	= 1	; Port A Data Register bit 1
+.equ	PA1	= 1	; For compatibility
+.equ	PORTA2	= 2	; Port A Data Register bit 2
+.equ	PA2	= 2	; For compatibility
+.equ	PORTA3	= 3	; Port A Data Register bit 3
+.equ	PA3	= 3	; For compatibility
+.equ	PORTA4	= 4	; Port A Data Register bit 4
+.equ	PA4	= 4	; For compatibility
+.equ	PORTA5	= 5	; Port A Data Register bit 5
+.equ	PA5	= 5	; For compatibility
+.equ	PORTA6	= 6	; Port A Data Register bit 6
+.equ	PA6	= 6	; For compatibility
+.equ	PORTA7	= 7	; Port A Data Register bit 7
+.equ	PA7	= 7	; For compatibility
+
+; DDRA - Port A Data Direction Register
+.equ	DDA0	= 0	; Data Direction Register, Port A, bit 0
+.equ	DDA1	= 1	; Data Direction Register, Port A, bit 1
+.equ	DDA2	= 2	; Data Direction Register, Port A, bit 2
+.equ	DDA3	= 3	; Data Direction Register, Port A, bit 3
+.equ	DDA4	= 4	; Data Direction Register, Port A, bit 4
+.equ	DDA5	= 5	; Data Direction Register, Port A, bit 5
+.equ	DDA6	= 6	; Data Direction Register, Port A, bit 6
+.equ	DDA7	= 7	; Data Direction Register, Port A, bit 7
+
+; PINA - Port A Input Pins
+.equ	PINA0	= 0	; Input Pins, Port A bit 0
+.equ	PINA1	= 1	; Input Pins, Port A bit 1
+.equ	PINA2	= 2	; Input Pins, Port A bit 2
+.equ	PINA3	= 3	; Input Pins, Port A bit 3
+.equ	PINA4	= 4	; Input Pins, Port A bit 4
+.equ	PINA5	= 5	; Input Pins, Port A bit 5
+.equ	PINA6	= 6	; Input Pins, Port A bit 6
+.equ	PINA7	= 7	; Input Pins, Port A bit 7
+
+
+; ***** PORTB ************************
+; PORTB - Port B Data Register
+.equ	PORTB0	= 0	; Port B Data Register bit 0
+.equ	PB0	= 0	; For compatibility
+.equ	PORTB1	= 1	; Port B Data Register bit 1
+.equ	PB1	= 1	; For compatibility
+.equ	PORTB2	= 2	; Port B Data Register bit 2
+.equ	PB2	= 2	; For compatibility
+.equ	PORTB3	= 3	; Port B Data Register bit 3
+.equ	PB3	= 3	; For compatibility
+.equ	PORTB4	= 4	; Port B Data Register bit 4
+.equ	PB4	= 4	; For compatibility
+.equ	PORTB5	= 5	; Port B Data Register bit 5
+.equ	PB5	= 5	; For compatibility
+.equ	PORTB6	= 6	; Port B Data Register bit 6
+.equ	PB6	= 6	; For compatibility
+.equ	PORTB7	= 7	; Port B Data Register bit 7
+.equ	PB7	= 7	; For compatibility
+
+; DDRB - Port B Data Direction Register
+.equ	DDB0	= 0	; Port B Data Direction Register bit 0
+.equ	DDB1	= 1	; Port B Data Direction Register bit 1
+.equ	DDB2	= 2	; Port B Data Direction Register bit 2
+.equ	DDB3	= 3	; Port B Data Direction Register bit 3
+.equ	DDB4	= 4	; Port B Data Direction Register bit 4
+.equ	DDB5	= 5	; Port B Data Direction Register bit 5
+.equ	DDB6	= 6	; Port B Data Direction Register bit 6
+.equ	DDB7	= 7	; Port B Data Direction Register bit 7
+
+; PINB - Port B Input Pins
+.equ	PINB0	= 0	; Port B Input Pins bit 0
+.equ	PINB1	= 1	; Port B Input Pins bit 1
+.equ	PINB2	= 2	; Port B Input Pins bit 2
+.equ	PINB3	= 3	; Port B Input Pins bit 3
+.equ	PINB4	= 4	; Port B Input Pins bit 4
+.equ	PINB5	= 5	; Port B Input Pins bit 5
+.equ	PINB6	= 6	; Port B Input Pins bit 6
+.equ	PINB7	= 7	; Port B Input Pins bit 7
+
+
+; ***** PORTC ************************
+; PORTC - Port C Data Register
+.equ	PORTC0	= 0	; Port C Data Register bit 0
+.equ	PC0	= 0	; For compatibility
+.equ	PORTC1	= 1	; Port C Data Register bit 1
+.equ	PC1	= 1	; For compatibility
+.equ	PORTC2	= 2	; Port C Data Register bit 2
+.equ	PC2	= 2	; For compatibility
+.equ	PORTC3	= 3	; Port C Data Register bit 3
+.equ	PC3	= 3	; For compatibility
+.equ	PORTC4	= 4	; Port C Data Register bit 4
+.equ	PC4	= 4	; For compatibility
+.equ	PORTC5	= 5	; Port C Data Register bit 5
+.equ	PC5	= 5	; For compatibility
+.equ	PORTC6	= 6	; Port C Data Register bit 6
+.equ	PC6	= 6	; For compatibility
+.equ	PORTC7	= 7	; Port C Data Register bit 7
+.equ	PC7	= 7	; For compatibility
+
+; DDRC - Port C Data Direction Register
+.equ	DDC0	= 0	; Port C Data Direction Register bit 0
+.equ	DDC1	= 1	; Port C Data Direction Register bit 1
+.equ	DDC2	= 2	; Port C Data Direction Register bit 2
+.equ	DDC3	= 3	; Port C Data Direction Register bit 3
+.equ	DDC4	= 4	; Port C Data Direction Register bit 4
+.equ	DDC5	= 5	; Port C Data Direction Register bit 5
+.equ	DDC6	= 6	; Port C Data Direction Register bit 6
+.equ	DDC7	= 7	; Port C Data Direction Register bit 7
+
+; PINC - Port C Input Pins
+.equ	PINC0	= 0	; Port C Input Pins bit 0
+.equ	PINC1	= 1	; Port C Input Pins bit 1
+.equ	PINC2	= 2	; Port C Input Pins bit 2
+.equ	PINC3	= 3	; Port C Input Pins bit 3
+.equ	PINC4	= 4	; Port C Input Pins bit 4
+.equ	PINC5	= 5	; Port C Input Pins bit 5
+.equ	PINC6	= 6	; Port C Input Pins bit 6
+.equ	PINC7	= 7	; Port C Input Pins bit 7
+
+
+; ***** PORTD ************************
+; PORTD - Port D Data Register
+.equ	PORTD0	= 0	; Port D Data Register bit 0
+.equ	PD0	= 0	; For compatibility
+.equ	PORTD1	= 1	; Port D Data Register bit 1
+.equ	PD1	= 1	; For compatibility
+.equ	PORTD2	= 2	; Port D Data Register bit 2
+.equ	PD2	= 2	; For compatibility
+.equ	PORTD3	= 3	; Port D Data Register bit 3
+.equ	PD3	= 3	; For compatibility
+.equ	PORTD4	= 4	; Port D Data Register bit 4
+.equ	PD4	= 4	; For compatibility
+.equ	PORTD5	= 5	; Port D Data Register bit 5
+.equ	PD5	= 5	; For compatibility
+.equ	PORTD6	= 6	; Port D Data Register bit 6
+.equ	PD6	= 6	; For compatibility
+.equ	PORTD7	= 7	; Port D Data Register bit 7
+.equ	PD7	= 7	; For compatibility
+
+; DDRD - Port D Data Direction Register
+.equ	DDD0	= 0	; Port D Data Direction Register bit 0
+.equ	DDD1	= 1	; Port D Data Direction Register bit 1
+.equ	DDD2	= 2	; Port D Data Direction Register bit 2
+.equ	DDD3	= 3	; Port D Data Direction Register bit 3
+.equ	DDD4	= 4	; Port D Data Direction Register bit 4
+.equ	DDD5	= 5	; Port D Data Direction Register bit 5
+.equ	DDD6	= 6	; Port D Data Direction Register bit 6
+.equ	DDD7	= 7	; Port D Data Direction Register bit 7
+
+; PIND - Port D Input Pins
+.equ	PIND0	= 0	; Port D Input Pins bit 0
+.equ	PIND1	= 1	; Port D Input Pins bit 1
+.equ	PIND2	= 2	; Port D Input Pins bit 2
+.equ	PIND3	= 3	; Port D Input Pins bit 3
+.equ	PIND4	= 4	; Port D Input Pins bit 4
+.equ	PIND5	= 5	; Port D Input Pins bit 5
+.equ	PIND6	= 6	; Port D Input Pins bit 6
+.equ	PIND7	= 7	; Port D Input Pins bit 7

pat80-io-devices/composite-pal-adapter/software/avr-assembly/fuses.conf

@@ -0,0 +1,4 @@
+fuses_lo = 0xAF
+fuses_hi = 0x99
+fuses_ext = 0xff
+lock_byte = 0xff

pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm

@@ -0,0 +1,142 @@
+; VIDEO COMPOSITE PAL IO DEVICE
+; Implemented following timings in http://blog.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
+
+.include "atmega1284definition.asm"
+
+; define constant
+.equ SYNC_PIN = PD7		; Sync pin is on Port D 7 (pin 21)
+.equ VIDEO_PIN = PD6	; Video pin is on Port D 6 (pin 20)
+
+; start vector
+.org 0x0000
+	rjmp	main			; jump to main label
+
+; main program
+main:
+	sbi	DDRD, SYNC_PIN		; set pin as output
+	sbi	DDRD, VIDEO_PIN		; set pin as output
+
+v_refresh_loop:
+	; start 5 long sync pulses
+	call long_sync
+	call long_sync
+	call long_sync
+	call long_sync
+	call long_sync
+	; end 5 long sync pulses
+
+	; start 5 short sync pulses
+	call short_sync
+	call short_sync
+	call short_sync
+	call short_sync
+	call short_sync
+	; end 5 short sync pulses
+
+	; start 304 picture lines
+	ldi r16, 2
+	h_picture_outer_loop:
+		ldi r17, 152	; line counter
+		h_picture_loop:
+			; start line sync: 4uS, 96 cycles @ 24Mhz
+			cbi	PORTD, SYNC_PIN	; sync goes low (0v)					; 2 cycle
+			ldi r18, 32													; 1 cycle
+			l_sync_pulse_loop: ; requires 3 cpu cycles
+				dec r18													; 1 cycle
+				brne l_sync_pulse_loop  								; 2 cycle if true, 1 if false
+			sbi	PORTD, SYNC_PIN	; sync goes high (0.3v)
+			; end line sync
+
+			; start back porch: 8uS, 192 cycles @ 24Mhz
+			ldi r18, 64													; 1 cycle
+			l_sync_back_porch_loop:
+				dec r18													; 1 cycle
+				brne l_sync_back_porch_loop  							; 2 cycle if true, 1 if false
+			; end back porch
+
+			; start image: 52uS, 1247 cycles @ 24Mhz
+			; 3 bande da 416 cicli
+
+			sbi	PORTD, VIDEO_PIN	; video goes high					; 2 cycle
+
+			ldi r18, 138													; 1 cycle
+			l_sync_video_loop1:
+				dec r18													; 1 cycle
+				brne l_sync_video_loop1  								; 2 cycle if true, 1 if false
+
+			cbi	PORTD, VIDEO_PIN	; video goes low
+
+			ldi r18, 137												; 1 cycle
+			l_sync_video_loop2:
+				dec r18													; 1 cycle
+				brne l_sync_video_loop2 								; 2 cycle if true, 1 if false
+
+			sbi	PORTD, VIDEO_PIN	; video goes high
+
+			ldi r18, 138												; 1 cycle
+			l_sync_video_loop3:
+				dec r18													; 1 cycle
+				brne l_sync_video_loop3  								; 2 cycle if true, 1 if false
+			cbi	PORTD, VIDEO_PIN	; video goes low
+
+			; end image
+
+			dec r17 ; decrement line counter
+			brne h_picture_loop	; if not 0, repeat h_picture_loop
+
+		dec r16 ; decrement outside counter
+		brne h_picture_outer_loop	; if not 0, repeat h_picture_loop
+	; end picture lines
+
+	; start 6 short sync pulses
+	call short_sync
+	call short_sync
+	call short_sync
+	call short_sync
+	call short_sync
+	; end 6 short sync pulses
+
+	jmp v_refresh_loop
+; end vertical refresh
+
+long_sync:
+	; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz)
+	cbi	PORTD, SYNC_PIN	; sync goes low (0v)					; 2 cycle
+
+	ldi r18, 120												; 1 cycle
+	long_sync_low_loop: ; requires 6 cpu cycles
+		nop														; 1 cycle
+		nop														; 1 cycle
+		nop														; 1 cycle
+		dec r18													; 1 cycle
+		brne long_sync_low_loop  								; 2 cycle if true, 1 if false
+
+	sbi	PORTD, SYNC_PIN	; sync goes high (0.3v)
+
+	ldi r18, 16													; 1 cycle
+	long_sync_high_loop: ; requires 3 cpu cycles
+		dec r18													; 1 cycle
+		brne long_sync_high_loop  								; 2 cycle if true, 1 if false
+
+	ret
+
+short_sync:
+	; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high
+	cbi	PORTD, SYNC_PIN	; sync goes low (0v)					; 2 cycle
+
+	ldi r18, 16													; 1 cycle
+	short_sync_low_loop: ; requires 3 cpu cycles
+		dec r18													; 1 cycle
+		brne long_sync_low_loop  								; 2 cycle if true, 1 if false
+
+	sbi	PORTD, SYNC_PIN	; sync goes high (0.3v)
+
+	ldi r18, 120												; 1 cycle
+	short_sync_high_loop: ; requires 6 cpu cycles
+		nop														; 1 cycle
+		nop														; 1 cycle
+		nop														; 1 cycle
+		dec r18													; 1 cycle
+		brne short_sync_high_loop  								; 2 cycle if true, 1 if false
+
+	ret

pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.eep.hex

@@ -0,0 +1 @@
+:00000001FF

pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.hex

@@ -0,0 +1,4 @@
+:020000020000FC
+:1000000000C0579A4F995F984F9B5F9A40E230E447
+:1000100020E82A95F1F73A95D9F74A95C1F7F2CF3A
+:00000001FF

pat80-io-devices/parallel-terminal/python/terminal_emulator.py

@@ -91,9 +91,11 @@ class TerminalEmulator:
             with open(path, "rb") as f:
                 byte = f.read(1)
                 while byte:
+                    # Check if terminal interface (Arduino) is busy
+                    ser.write(b'\x01')  # COMMAND_BUFFER
+                    ser.read()
                     ser.write(byte)
                     byte = f.read(1)
-                    time.sleep(self.SYNC_SLEEP)
         except IOError as e:
             w.move(0,0)
             w.clrtoeol()