Working timer1, but wrong timings
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7c07014b75
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@ -39,10 +39,11 @@
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; start vector
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; start vector
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.org 0x0000
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.org 0x0000
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rjmp main ; jump to main label
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rjmp main ; reset vector: jump to main label
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.org 0x0012
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.org 0x001E
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rjmp on_int1 ; interrupt for timer 1 overflow
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rjmp on_tim1_ovf ; interrupt for timer 1 overflow
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.org 0x40
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; main program
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; main program
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main:
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main:
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; pins setup
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; pins setup
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@ -70,27 +71,20 @@ main:
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cpi r26, 0b11000000
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cpi r26, 0b11000000
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brne load_mem_loop ; if not 0, repeat h_picture_loop
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brne load_mem_loop ; if not 0, repeat h_picture_loop
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; timer setup (use 16-bit counter TC1)
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; *** timer setup (use 16-bit counter TC1) ***
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; The Power Reduction TC1 and TC3 bits in the Power Reduction Registers (PRR0.PRTIM1 and
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; The Power Reduction TC1 and TC3 bits in the Power Reduction Registers (PRR0.PRTIM1 and
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; PRR1.PRTIM3) must be written to zero to enable the TC1 and TC3 module.
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; PRR1.PRTIM3) must be written to zero to enable the TC1 and TC3 module.
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ldi r16, 0b00001000
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ldi r16, 0b00000000
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sts PRR0, r16
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sts PRR0, r16
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ldi r16, 0b00000001
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; Set timer prescaler to 1:1
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sts PRR1, r16
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LDI r16,0b00000001
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; Set TCNT1 (timer counter) to 0xFF00 (the timer will trigger soon)
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ser r27
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sts TCNT1H,r27
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clr r26
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sts TCNT1L,r26
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; Set prescaler to 1:1 (TCCR1B is XXXXX001)
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ldi r16, 0b00000001
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sts TCCR1B,r16
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sts TCCR1B,r16
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; Enable timer1 overflow interrupt(TOIE1): the interrupt 1 will be fired when timer resets
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; Enambe timer1 overflow interrupt
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ldi r16, 0b00000100
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LDI r16,0b00000001
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sts TIMSK1, r16
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STS TIMSK1,r16
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; The Global Interrupt Enable bit must be set for the interrupts to be enabled.
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; Enable interrupts globally
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ldi r16, 0b10000000
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SEI
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sts SREG, r16
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; Timer setup completed.
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; loop forever
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; loop forever
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forever:
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forever:
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@ -98,8 +92,8 @@ main:
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; ********* FUNCTIONS CALLED BY INTERRUPT ***********
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; ********* FUNCTIONS CALLED BY INTERRUPT ***********
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on_int1:
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on_tim1_ovf:
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; called by timer 1 two times per line (every 32 uS) during hsync. Disabled while drawing picture.
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; called by timer 1 two times per line (every 32 uS) during hsync, unless drawing picture.
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; if r25 >= 32 then r25=0
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; if r25 >= 32 then r25=0
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cpi r25, 32
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cpi r25, 32
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@ -112,6 +106,7 @@ on_int1:
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cpi r25, 10 ; 5-9: short sync
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cpi r25, 10 ; 5-9: short sync
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breq draw_picture ; 10: draw picture
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breq draw_picture ; 10: draw picture
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jmp short_sync ; 11-16: short_sync
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jmp short_sync ; 11-16: short_sync
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; reti is at end of all previous jumps
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draw_picture:
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draw_picture:
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; increment status
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; increment status
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