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Working timer1, but wrong timings

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Daniele Verducci su MatissePenguin 2021-01-16 19:54:32 +01:00
parent 7c07014b75
commit cf3956356e
1 changed files with 24 additions and 29 deletions
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39
pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm
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@ -39,10 +39,11 @@
; start vector
.org 0x0000
rjmp main ; jump to main label
.org 0x0012
rjmp on_int1 ; interrupt for timer 1 overflow
rjmp main ; reset vector: jump to main label
.org 0x001E
rjmp on_tim1_ovf ; interrupt for timer 1 overflow
.org 0x40
; main program
main:
; pins setup
@ -70,27 +71,20 @@ main:
cpi r26, 0b11000000
brne load_mem_loop ; if not 0, repeat h_picture_loop
; timer setup (use 16-bit counter TC1)
; *** timer setup (use 16-bit counter TC1) ***
; The Power Reduction TC1 and TC3 bits in the Power Reduction Registers (PRR0.PRTIM1 and
; PRR1.PRTIM3) must be written to zero to enable the TC1 and TC3 module.
ldi r16, 0b00001000
ldi r16, 0b00000000
sts PRR0, r16
ldi r16, 0b00000001
sts PRR1, r16
; Set TCNT1 (timer counter) to 0xFF00 (the timer will trigger soon)
ser r27
sts TCNT1H,r27
clr r26
sts TCNT1L,r26
; Set prescaler to 1:1 (TCCR1B is XXXXX001)
ldi r16, 0b00000001
; Set timer prescaler to 1:1
LDI r16,0b00000001
sts TCCR1B,r16
; Enable timer1 overflow interrupt(TOIE1): the interrupt 1 will be fired when timer resets
ldi r16, 0b00000100
sts TIMSK1, r16
; The Global Interrupt Enable bit must be set for the interrupts to be enabled.
ldi r16, 0b10000000
sts SREG, r16
; Enambe timer1 overflow interrupt
LDI r16,0b00000001
STS TIMSK1,r16
; Enable interrupts globally
SEI
; Timer setup completed.
; loop forever
forever:
@ -98,8 +92,8 @@ main:
; ********* FUNCTIONS CALLED BY INTERRUPT ***********
on_int1:
; called by timer 1 two times per line (every 32 uS) during hsync. Disabled while drawing picture.
on_tim1_ovf:
; called by timer 1 two times per line (every 32 uS) during hsync, unless drawing picture.
; if r25 >= 32 then r25=0
cpi r25, 32
@ -112,6 +106,7 @@ on_int1:
cpi r25, 10 ; 5-9: short sync
breq draw_picture ; 10: draw picture
jmp short_sync ; 11-16: short_sync
; reti is at end of all previous jumps
draw_picture:
; increment status