Commit Graph

4 Commits

Author SHA1 Message Date
Daniele Verducci (ZenPenguin)
faef987494 WIP UART sampling at mid clock 2021-03-15 07:30:36 +01:00
Daniele Verducci su MatissePenguin
186689fd5c UART: Thinking how to delay sampling to mid clock 2021-03-06 14:09:38 +01:00
Daniele Verducci su MatissePenguin
35cb230ea6 Working UART simulation without rx clock sync 2021-03-06 12:59:01 +01:00
Daniele Verducci (ZenPenguin)
f414a14c09 WIP UART Rx simulation with Logisim 2021-03-05 08:58:22 +01:00