Daniele Verducci (ZenPenguin)
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aa844687c8
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Ready for github publishing
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2021-07-11 09:49:42 +02:00 |
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Daniele Verducci (ZenPenguin)
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faef987494
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WIP UART sampling at mid clock
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2021-03-15 07:30:36 +01:00 |
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Daniele Verducci su MatissePenguin
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186689fd5c
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UART: Thinking how to delay sampling to mid clock
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2021-03-06 14:09:38 +01:00 |
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Daniele Verducci su MatissePenguin
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35cb230ea6
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Working UART simulation without rx clock sync
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2021-03-06 12:59:01 +01:00 |
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Daniele Verducci (ZenPenguin)
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f414a14c09
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WIP UART Rx simulation with Logisim
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2021-03-05 08:58:22 +01:00 |
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