1583 lines
37 KiB
NASM
1583 lines
37 KiB
NASM
; VIDEO COMPOSITE PAL IO DEVICE
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; Implemented following timings in http://blog.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
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; Every line, for 52 times, it loads a byte from memory into PORTA register and then shifts the byte to the left to show another bit (do it 7 times)
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; This also displays byte's MSB pixel "for free", as the video pin is PD7 (last bit of PORTA).
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;
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; INTERFACING WITH PAT80:
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; Use PortB as data port. Before writing anything, issue a read (pin RW HIGH) and check the busy pin on the data port.
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; If the busy pin is high, retry reading until goes low. When the busy pin goes low, we have... TODO
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;
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; ELECTRONICALLY:
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; The data port D0 (= PB0) is tied to ground with a 1KOhm resistance. When the MC is busy drawing the screen, the data port is in
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; high impedance state, so that avoids causing bus contention, but when read returns a 0bXXXXXXX0 byte. When the MC starts vsync,
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; begins checking the port for data... TODO
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;
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; PINS:
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; Video pin: PA0 (pin 1)
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; Sync pin: PC0 (pin 22)
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; Debug hsync pin: PC1 (pin 23)
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;
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; STATUS TABLE:
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; R25 (STATUS): Current status (what the interrupt should do when fired):
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; 0-9 = long sync
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; 10-19 = short sync
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; 20 = draw lines (draw 304 lines complete with line sync and back porch, then start short
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; sync: sync pin low and next interrupt after 2uS)
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; 21-32 = short sync
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; 33-255 = invalid state or screen draw finished: set to 0 and restart from first long sync start
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.include "m1284def.inc"
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; registers
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.def A = r0 ; accumulator
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.def STATUS = r25 ; signal status (see STATUS TABLE)
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; define constant
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.equ SYNC_PIN = PC0 ; Sync pin (pin 22)
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.equ DEBUG_PIN = PC1 ; DEBUG: Single vertical sync pulse to trigger oscilloscope (pin 23)
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.equ TIMER_DELAY_30US = 65535 - 690 ; 719 cycles @ 24Mhz (minus overhead)
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.equ TIMER_DELAY_2US = 65535 - 17 ; 48 cycles @ 24Mhz (minus overhead)
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; memory
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.equ FRAMEBUFFER = 0x100
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; start vector
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.org 0x0000
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rjmp main ; reset vector: jump to main label
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.org 0x001E
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rjmp on_tim1_ovf ; interrupt for timer 1 overflow
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.org 0x40
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; main program
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main:
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; pins setup
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sbi DDRC, SYNC_PIN ; set pin as output
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sbi DDRC, DEBUG_PIN ; set pin as output
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ldi r16, 0xFF
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out DDRA, r16 ; set port as output (contains video pin)
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; *** Load data into ram ***
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; Set X to 0x0100
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ldi r27, high(FRAMEBUFFER<<1)
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ldi r26, low(FRAMEBUFFER<<1)
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; Set Z to 0x1000 (cat image)
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ldi r31, high(CAT_IMAGE<<1)
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ldi r30, low(CAT_IMAGE<<1)
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load_mem_loop:
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lpm r17, Z+
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;ldi r17, 0b00001111
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st X+, r17
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; if reached the last framebuffer byte, exit cycle
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cpi r27, 0b00111110
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brne load_mem_loop ; if not 0, repeat h_picture_loop
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cpi r26, 0b11000000
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brne load_mem_loop ; if not 0, repeat h_picture_loop
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; *** timer setup (use 16-bit counter TC1) ***
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; The Power Reduction TC1 and TC3 bits in the Power Reduction Registers (PRR0.PRTIM1 and
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; PRR1.PRTIM3) must be written to zero to enable the TC1 and TC3 module.
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ldi r16, 0b00000000
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sts PRR0, r16
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; Set timer prescaler to 1:1
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LDI r16,0b00000001
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sts TCCR1B,r16
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; Enambe timer1 overflow interrupt
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LDI r16,0b00000001
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STS TIMSK1,r16
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; Enable interrupts globally
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SEI
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; Timer setup completed.
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; loop forever
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forever:
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jmp forever
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; ********* FUNCTIONS CALLED BY INTERRUPT ***********
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on_tim1_ovf:
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; debug
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; sbi PORTC, DEBUG_PIN ; high
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; cbi PORTC, DEBUG_PIN ; low
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; ; set timer in 30uS (reset timer counter)
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; ldi r27, high(TIMER_DELAY_30US)
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; ldi r26, low(TIMER_DELAY_30US)
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; sts TCNT1H,r27
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; sts TCNT1L,r26
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; reti
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; debug
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; called by timer 1 two times per line (every 32 uS) during hsync, unless drawing picture.
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inc STATUS
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; if STATUS >= 33 then STATUS=0
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cpi STATUS, 35 ; TODO: Added a seventh sync pulse at end of screen because at the first short sync after the image, the timer doesn't tick at the right time
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brlo switch_status
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clr STATUS
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; check status and decide what to do
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switch_status:
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cpi STATUS, 10
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brlo long_sync ; 0-9: long sync
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cpi STATUS, 20
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breq draw_picture ; 20: draw picture
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jmp short_sync ; 10-19 or 21-32: short_sync
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; reti is at end of all previous jumps
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draw_picture:
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; set X register to framebuffer start 0x0100
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; (set it a byte before, because it will be incremented at first)
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clr r27
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ldi r26, 0xFF
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; start 304 picture lines
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ldi r17, 152 ; line counter
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h_picture_loop:
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; debug
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; sbi PORTC, DEBUG_PIN ; high
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; cbi PORTC, DEBUG_PIN ; low
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; debug
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; ***************** DRAW FIRST LINE *********************
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; **** start line sync: 4uS, 96 cycles @ 24Mhz
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; video pin goes low before sync
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clr r19 ; 1 cycle
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out PORTA, r19 ; 1 cycle
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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ldi r18, 31 ; 1 cycle
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l_sync_pulse_loop: ; requires 3 cpu cycles
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dec r18 ; 1 cycle
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brne l_sync_pulse_loop ; 2 cycle if true, 1 if false
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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; **** end line sync
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; **** start line back porch: 8uS, 192 cycles @ 24Mhz
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; leave time at the end for line setup and draw_line call
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ldi r18, 62 ; 1 cycle
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l_sync_back_porch_loop:
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dec r18 ; 1 cycle
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brne l_sync_back_porch_loop ; 2 cycle if true, 1 if false
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; **** end back porch
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call draw_line ; 3 cycles (+ 3 to come back to on_line_drawn)
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; **** draws line pixels: 52uS, 1248 cycles @ 24Mhz ****
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; ***************** DRAW SECOND LINE *********************
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; **** start line sync: 4uS, 96 cycles @ 24Mhz
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; video pin goes low before sync
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clr r19 ; 1 cycle
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out PORTA, r19 ; 1 cycle
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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ldi r18, 31 ; 1 cycle
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l_sync_pulse_loop2: ; requires 3 cpu cycles
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dec r18 ; 1 cycle
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brne l_sync_pulse_loop2 ; 2 cycle if true, 1 if false
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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; **** end line sync
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; **** start line back porch: 8uS, 192 cycles @ 24Mhz
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; leave time at the end for line setup and draw_line call
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ldi r18, 62 ; 1 cycle
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l_sync_back_porch_loop2:
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dec r18 ; 1 cycle
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brne l_sync_back_porch_loop2 ; 2 cycle if true, 1 if false
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; **** end back porch
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call draw_line ; 3 cycles (+ 3 to come back to on_line_drawn)
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; **** draws line pixels: 52uS, 1248 cycles @ 24Mhz ****
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; debug
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; sbi PORTC, DEBUG_PIN ; high
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; cbi PORTC, DEBUG_PIN ; low
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; debug
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dec r17 ; decrement line countr ; 1 cycle
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brne h_picture_loop ; if not 0, repeat h_picture_loop ; 2 cycle if true, 1 if false
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; end picture lines
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; video pin goes low before sync
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clr r19 ; 1 cycle
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out PORTA, r19 ; 1 cycle
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; debug
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; sbi PORTC, DEBUG_PIN ; high
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; cbi PORTC, DEBUG_PIN ; low
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; debug
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; immediately start first end-screen short sync:
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inc STATUS
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jmp short_sync
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; reti is in short_sync
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; end draw_picture
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long_sync:
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; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz)
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sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
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jmp long_sync_end
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; sync pin is high (sync is not occuring)
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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; set timer in 30uS (reset timer counter)
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ldi r27, high(TIMER_DELAY_30US)
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ldi r26, low(TIMER_DELAY_30US)
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sts TCNT1H,r27
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sts TCNT1L,r26
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reti
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long_sync_end:
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; sync pin is low (sync is occuring)
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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; set timer in 2uS:
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ldi r27, high(TIMER_DELAY_2US)
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ldi r26, low(TIMER_DELAY_2US)
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sts TCNT1H,r27
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sts TCNT1L,r26
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reti
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short_sync:
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; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz)
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sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
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jmp short_sync_end
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; sync pin is high (sync is not occuring)
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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; set timer in 2uS (reset timer counter)
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ldi r27, high(TIMER_DELAY_2US)
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ldi r26, low(TIMER_DELAY_2US)
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sts TCNT1H,r27
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sts TCNT1L,r26
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reti
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short_sync_end:
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; sync pin is low (sync is occuring)
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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; set timer in 30uS:
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ldi r27, high(TIMER_DELAY_30US)
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ldi r26, low(TIMER_DELAY_30US)
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sts TCNT1H,r27
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sts TCNT1L,r26
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reti
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draw_line:
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; NO loops, as this is time-strict
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; 52 chunks of 8 pixels
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; chunk 1
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 2
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 3
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 4
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 5
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 6
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 7
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 8
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 9
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 10
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 11
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 12
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 13
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 14
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 15
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 16
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 17
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 18
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 19
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 20
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 21
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 22
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 23
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 24
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 25
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 26
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 27
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 28
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 29
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 30
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 31
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 32
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 33
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 34
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 35
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 36
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 37
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 38
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 39
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 40
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 41
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 42
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 43
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 44
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 45
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 46
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 47
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 48
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 49
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 50
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 51
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 52
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
ret
|
|
|
|
|
|
.include "cat.asm" |