1479 lines
34 KiB
NASM
1479 lines
34 KiB
NASM
; *******************************************
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; * PAT80 COMPOSITE PAL VIDEO ADAPTER *
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; * Video generator module *
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; *******************************************
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; This module generates a Composite PAL monochrome signal with a resolution
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; of 416x304 pixels (= 52x38 characters). The signal is generated using 16-bit
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; Timer1 and interrupts.
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; How does it work:
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; The screen draw is divided in phases. Every phase does something. I.e. phases 0 to 9
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; represents the first 5 long syncs:
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; (sync goes low, wait 30uS, sync goes high, wait 2uS) x 5 times = 10 phases
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; When the interrupt is called, it uses register r25 (STATUS) to decide what to do.
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;
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; STATUS TABLE:
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; R25 (STATUS): Current status (what the interrupt should do when fired):
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; 0-9 = long sync
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; 10-19 = short sync
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; 20 = draw lines (draw 304 lines complete with line sync and back porch, then start short
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; sync: sync pin low and next interrupt after 2uS)
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; 21-32 = short sync
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; 33-255 = invalid state or screen draw finished: set to 0 and restart from first long sync start
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.equ TIMER_DELAY_30US = 65535 - 690 ; 719 cycles @ 24Mhz (minus overhead)
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.equ TIMER_DELAY_2US = 65535 - 17 ; 48 cycles @ 24Mhz (minus overhead)
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; ********* FUNCTIONS CALLED BY INTERRUPT ***********
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on_tim1_ovf:
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; called by timer 1 two times per line (every 32 uS) during hsync, unless drawing picture.
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inc STATUS
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; if STATUS >= 33 then STATUS=0
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cpi STATUS, 35 ; TODO: Added a seventh sync pulse at end of screen because at the first short sync after the image, the timer doesn't tick at the right time
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brlo switch_status
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clr STATUS
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; check status and decide what to do
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switch_status:
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cpi STATUS, 10
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brlo long_sync ; 0-9: long sync
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cpi STATUS, 20
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breq draw_picture ; 20: draw picture
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jmp short_sync ; 10-19 or 21-32: short_sync
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; reti is at end of all previous jumps
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draw_picture:
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; set X register to framebuffer start 0x0100
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; (set it a byte before, because it will be incremented at first)
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clr r27
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ldi r26, 0xFF
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; start 304 picture lines
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ldi r17, 152 ; line counter
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h_picture_loop:
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; ***************** DRAW FIRST LINE *********************
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; **** start line sync: 4uS, 96 cycles @ 24Mhz
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; video pin goes low before sync
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clr r19 ; 1 cycle
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out PORTA, r19 ; 1 cycle
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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ldi r18, 31 ; 1 cycle
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l_sync_pulse_loop: ; requires 3 cpu cycles
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dec r18 ; 1 cycle
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brne l_sync_pulse_loop ; 2 cycle if true, 1 if false
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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; **** end line sync
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; **** start line back porch: 8uS, 192 cycles @ 24Mhz
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; leave time at the end for line setup and draw_line call
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ldi r18, 62 ; 1 cycle
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l_sync_back_porch_loop:
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dec r18 ; 1 cycle
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brne l_sync_back_porch_loop ; 2 cycle if true, 1 if false
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; **** end back porch
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call draw_line ; 3 cycles (+ 3 to come back to on_line_drawn)
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; **** draws line pixels: 52uS, 1248 cycles @ 24Mhz ****
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; ***************** DRAW SECOND LINE *********************
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; **** start line sync: 4uS, 96 cycles @ 24Mhz
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; video pin goes low before sync
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clr r19 ; 1 cycle
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out PORTA, r19 ; 1 cycle
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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ldi r18, 31 ; 1 cycle
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l_sync_pulse_loop2: ; requires 3 cpu cycles
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dec r18 ; 1 cycle
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brne l_sync_pulse_loop2 ; 2 cycle if true, 1 if false
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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; **** end line sync
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; **** start line back porch: 8uS, 192 cycles @ 24Mhz
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; leave time at the end for line setup and draw_line call
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ldi r18, 62 ; 1 cycle
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l_sync_back_porch_loop2:
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dec r18 ; 1 cycle
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brne l_sync_back_porch_loop2 ; 2 cycle if true, 1 if false
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; **** end back porch
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call draw_line ; 3 cycles (+ 3 to come back to on_line_drawn)
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; **** draws line pixels: 52uS, 1248 cycles @ 24Mhz ****
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dec r17 ; decrement line countr ; 1 cycle
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brne h_picture_loop ; if not 0, repeat h_picture_loop ; 2 cycle if true, 1 if false
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; end picture lines
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; video pin goes low before sync
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clr r19 ; 1 cycle
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out PORTA, r19 ; 1 cycle
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; immediately start first end-screen short sync:
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inc STATUS
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jmp short_sync
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; reti is in short_sync
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; end draw_picture
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long_sync:
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; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz)
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sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
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jmp long_sync_end
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; sync pin is high (sync is not occuring)
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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; set timer in 30uS (reset timer counter)
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ldi r27, high(TIMER_DELAY_30US)
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ldi r26, low(TIMER_DELAY_30US)
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sts TCNT1H,r27
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sts TCNT1L,r26
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reti
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long_sync_end:
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; sync pin is low (sync is occuring)
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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; set timer in 2uS:
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ldi r27, high(TIMER_DELAY_2US)
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ldi r26, low(TIMER_DELAY_2US)
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sts TCNT1H,r27
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sts TCNT1L,r26
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reti
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short_sync:
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; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz)
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sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
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jmp short_sync_end
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; sync pin is high (sync is not occuring)
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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; set timer in 2uS (reset timer counter)
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ldi r27, high(TIMER_DELAY_2US)
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ldi r26, low(TIMER_DELAY_2US)
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sts TCNT1H,r27
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sts TCNT1L,r26
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reti
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short_sync_end:
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; sync pin is low (sync is occuring)
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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; set timer in 30uS:
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ldi r27, high(TIMER_DELAY_30US)
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ldi r26, low(TIMER_DELAY_30US)
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sts TCNT1H,r27
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sts TCNT1L,r26
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reti
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draw_line:
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; NO loops, as this is time-strict
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; 52 chunks of 8 pixels
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; chunk 1
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 2
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 3
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 4
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 5
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 6
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 7
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 8
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 9
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 10
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 11
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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; chunk 12
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
|
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out PORTA, A ; 1 cycle
|
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nop ; 1 cycle
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lsr A ; 1 cycle
|
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out PORTA, A ; 1 cycle
|
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nop ; 1 cycle
|
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lsr A ; 1 cycle
|
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
|
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
|
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out PORTA, A ; 1 cycle
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|
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; chunk 13
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
|
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nop ; 1 cycle
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lsr A ; 1 cycle
|
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out PORTA, A ; 1 cycle
|
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nop ; 1 cycle
|
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lsr A ; 1 cycle
|
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out PORTA, A ; 1 cycle
|
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nop ; 1 cycle
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lsr A ; 1 cycle
|
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
|
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
|
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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|
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; chunk 14
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
|
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lsr A ; 1 cycle
|
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out PORTA, A ; 1 cycle
|
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nop ; 1 cycle
|
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lsr A ; 1 cycle
|
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out PORTA, A ; 1 cycle
|
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nop ; 1 cycle
|
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lsr A ; 1 cycle
|
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out PORTA, A ; 1 cycle
|
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nop ; 1 cycle
|
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lsr A ; 1 cycle
|
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out PORTA, A ; 1 cycle
|
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|
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; chunk 15
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ld A, X+ ; load pixel ; 2 cycles
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out PORTA, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out PORTA, A ; 1 cycle
|
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nop ; 1 cycle
|
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lsr A ; 1 cycle
|
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out PORTA, A ; 1 cycle
|
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nop ; 1 cycle
|
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lsr A ; 1 cycle
|
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out PORTA, A ; 1 cycle
|
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nop ; 1 cycle
|
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lsr A ; 1 cycle
|
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out PORTA, A ; 1 cycle
|
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nop ; 1 cycle
|
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lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 16
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 17
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 18
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 19
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 20
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 21
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 22
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 23
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 24
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 25
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 26
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 27
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 28
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 29
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 30
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 31
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 32
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 33
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 34
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 35
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 36
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 37
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 38
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 39
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 40
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 41
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 42
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 43
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 44
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 45
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 46
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 47
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 48
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 49
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 50
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 51
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
; chunk 52
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out PORTA, A ; 1 cycle
|
|
|
|
ret
|