1512 lines
36 KiB
NASM
1512 lines
36 KiB
NASM
; VIDEO COMPOSITE PAL IO DEVICE
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; Implemented following timings in http://blog.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
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; Every line, for 52 times, it loads a byte from memory into PORTD register and then shifts the byte to the left to show another bit (do it 7 times)
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; This also displays byte's MSB pixel "for free", as the video pin is PD7 (last bit of PORTD).
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.include "atmega1284definition.asm"
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; define constant
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.equ SYNC_PIN = PC0 ; Sync pin (pin 22)
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.equ VIDEO_PIN = PD7 ; Video pin (pin 21)
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.equ DEBUG_PIN = PC1 ; DEBUG: Single vertical sync pulse to trigger oscilloscope (pin 23)
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; memory
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.equ FRAMEBUFFER = 0x100
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; start vector
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.org 0x0000
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rjmp main ; jump to main label
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; main program
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main:
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sbi DDRC, SYNC_PIN ; set pin as output
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sbi DDRC, DEBUG_PIN ; set pin as output
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ldi r16, 0xFF
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out DDRD, r16 ; set port as output
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;*** Load data into ram ***
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; Set X to 0x0100
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ldi r27, high(FRAMEBUFFER<<1)
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ldi r26, low(FRAMEBUFFER<<1)
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; Set Z to 0x1000 (cat image)
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ldi r31, high(CAT_IMAGE<<1)
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ldi r30, low(CAT_IMAGE<<1)
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load_mem_loop:
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lpm r17, Z+
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;ldi r17, 0b00001111
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st X+, r17
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; if reached the last framebuffer byte, exit cycle
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cpi r27, 0b00111110
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brne load_mem_loop ; if not 0, repeat h_picture_loop
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cpi r26, 0b11000000
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brne load_mem_loop ; if not 0, repeat h_picture_loop
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v_refresh_loop:
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; set X register to framebuffer start 0x0100
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; (set it a byte before, because it will be incremented at first)
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clr r27
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ldi r26, 0xFF
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; start 5 long sync pulses
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call long_sync
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call long_sync
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call long_sync
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call long_sync
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call long_sync
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; end 5 long sync pulses
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; start 5 short sync pulses
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call short_sync
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call short_sync
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call short_sync
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call short_sync
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call short_sync
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; end 5 short sync pulses
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; start 304 picture lines
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ldi r17, 152 ; line counter
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h_picture_loop:
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; debug
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; sbi PORTC, DEBUG_PIN ; high
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; cbi PORTC, DEBUG_PIN ; low
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; debug
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; ***************** DRAW FIRST LINE *********************
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; **** start line sync: 4uS, 96 cycles @ 24Mhz
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cbi PORTD, VIDEO_PIN ; video pin goes low before sync ; 2 cycles
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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ldi r18, 31 ; 1 cycle
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l_sync_pulse_loop: ; requires 3 cpu cycles
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dec r18 ; 1 cycle
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brne l_sync_pulse_loop ; 2 cycle if true, 1 if false
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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; **** end line sync
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; **** start line back porch: 8uS, 192 cycles @ 24Mhz
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; leave time at the end for line setup and draw_line call
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ldi r18, 62 ; 1 cycle
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l_sync_back_porch_loop:
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dec r18 ; 1 cycle
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brne l_sync_back_porch_loop ; 2 cycle if true, 1 if false
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; **** end back porch
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call draw_line ; 3 cycles (+ 3 to come back to on_line_drawn)
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; **** draws line pixels: 52uS, 1248 cycles @ 24Mhz ****
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; ***************** DRAW SECOND LINE *********************
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; **** start line sync: 4uS, 96 cycles @ 24Mhz
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cbi PORTD, VIDEO_PIN ; video pin goes low before sync ; 2 cycles
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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ldi r18, 31 ; 1 cycle
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l_sync_pulse_loop2: ; requires 3 cpu cycles
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dec r18 ; 1 cycle
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brne l_sync_pulse_loop2 ; 2 cycle if true, 1 if false
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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; **** end line sync
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; **** start line back porch: 8uS, 192 cycles @ 24Mhz
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; leave time at the end for line setup and draw_line call
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ldi r18, 62 ; 1 cycle
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l_sync_back_porch_loop2:
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dec r18 ; 1 cycle
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brne l_sync_back_porch_loop2 ; 2 cycle if true, 1 if false
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; **** end back porch
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call draw_line ; 3 cycles (+ 3 to come back to on_line_drawn)
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; **** draws line pixels: 52uS, 1248 cycles @ 24Mhz ****
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; debug
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; sbi PORTC, DEBUG_PIN ; high
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; cbi PORTC, DEBUG_PIN ; low
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; debug
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dec r17 ; decrement line countr ; 1 cycle
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brne h_picture_loop ; if not 0, repeat h_picture_loop ; 2 cycle if true, 1 if false
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; end picture lines
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cbi PORTD, VIDEO_PIN ; video pin goes low before sync ; 2 cycles
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; start 6 short sync pulses
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call short_sync
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call short_sync
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call short_sync
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call short_sync
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call short_sync
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call short_sync
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; end 6 short sync pulses
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; debug
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; sbi PORTC, DEBUG_PIN ; high
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; cbi PORTC, DEBUG_PIN ; low
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; debug
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jmp v_refresh_loop
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; end vertical refresh
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long_sync:
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; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz)
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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ldi r18, 120 ; 1 cycle
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long_sync_low_loop: ; requires 6 cpu cycles
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nop ; 1 cycle
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nop ; 1 cycle
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nop ; 1 cycle
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dec r18 ; 1 cycle
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brne long_sync_low_loop ; 2 cycle if true, 1 if false
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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ldi r18, 15 ; 1 cycle
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long_sync_high_loop: ; requires 3 cpu cycles
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dec r18 ; 1 cycle
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brne long_sync_high_loop ; 2 cycle if true, 1 if false
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ret
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short_sync:
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; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz)
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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ldi r18, 15 ; 1 cycle
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short_sync_low_loop: ; requires 3 cpu cycles
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dec r18 ; 1 cycle
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brne short_sync_low_loop ; 2 cycle if true, 1 if false
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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ldi r18, 120 ; 1 cycle
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short_sync_high_loop: ; requires 6 cpu cycles
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nop ; 1 cycle
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nop ; 1 cycle
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nop ; 1 cycle
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dec r18 ; 1 cycle
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brne short_sync_high_loop ; 2 cycle if true, 1 if false
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ret
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draw_line:
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; NO loops, as this is time-strict
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; 52 chunks of 8 pixels
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; chunk 1
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ld r19, X+ ; load pixel ; 2 cycles
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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; chunk 2
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ld r19, X+ ; load pixel ; 2 cycles
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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; chunk 3
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ld r19, X+ ; load pixel ; 2 cycles
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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; chunk 4
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ld r19, X+ ; load pixel ; 2 cycles
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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; chunk 5
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ld r19, X+ ; load pixel ; 2 cycles
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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; chunk 6
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ld r19, X+ ; load pixel ; 2 cycles
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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; chunk 7
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ld r19, X+ ; load pixel ; 2 cycles
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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; chunk 8
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ld r19, X+ ; load pixel ; 2 cycles
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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; chunk 9
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ld r19, X+ ; load pixel ; 2 cycles
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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; chunk 10
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ld r19, X+ ; load pixel ; 2 cycles
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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; chunk 11
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ld r19, X+ ; load pixel ; 2 cycles
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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; chunk 12
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ld r19, X+ ; load pixel ; 2 cycles
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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; chunk 13
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ld r19, X+ ; load pixel ; 2 cycles
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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; chunk 14
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ld r19, X+ ; load pixel ; 2 cycles
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
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lsl r19 ; 1 cycle
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out PORTD, r19 ; 1 cycle
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nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 15
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 16
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 17
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 18
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 19
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 20
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 21
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 22
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 23
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 24
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 25
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 26
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 27
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 28
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 29
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 30
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 31
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 32
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 33
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 34
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 35
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 36
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 37
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 38
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 39
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 40
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 41
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 42
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 43
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 44
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 45
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 46
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 47
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 48
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 49
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 50
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 51
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
; chunk 52
|
|
ld r19, X+ ; load pixel ; 2 cycles
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsl r19 ; 1 cycle
|
|
out PORTD, r19 ; 1 cycle
|
|
|
|
ret
|
|
|
|
|
|
.include "cat.asm" |