92 lines
4.6 KiB
NASM
92 lines
4.6 KiB
NASM
; PS/2 Keyboard driver
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; @language: Z80 ASM
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;
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;
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; This file is part of Pat80 Memory Monitor.
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;
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; Pat80 Memory Monitor is free software: you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation, either version 3 of the License, or
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; (at your option) any later version.
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;
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; Pat80 Memory Monitor is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with Pat80 Memory Monitor. If not, see <http://www.gnu.org/licenses/>.
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;
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;
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; Based on PS/2 protocol as documented on http://www.lucadavidian.com/2017/11/15/interfacing-ps2-keyboard-to-a-microcontroller/
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;
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; The CLK and Data pin of the PS/2 keyboard are fed into two cascated serial-in parallel-out shift registers.
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; Their outputs are connected to the Pat80 data bus via a buffer activated by the selected
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; I/O EN signal and their RESET is connected to I/O Address line 0 of the keyboard I/O port.
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; Being RESET active low, they will be erased when the PAT80 reads (or writes) anything at address 0
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; of the keyboard I/0 port.
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;
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; Thus, the read cycle is:
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; - Read address 1 of the I/O port (the data bus will contain read keycode)
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; - Read address 0 of the I/O port (the shift registers will be reset)
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; The read keycode must be interpreted based on PS/2 Scan Codeset 2
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;
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; NOTE: The keyboard controller circuit throws away the MSB (uses only the lower 7 bits), because this allows
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; for using a single buffer chip instead of two (the freed up line is used by the PAT80 to reset the shift
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; registers). This means that the few keys with keycodes > 0x0F are not readable and that the break code is
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; seen by PAT80 not as 0xF0, but 0x70. This also means that the 0 of numeric keypad on extended keyboards will
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; behave strangely (will drop next pressed key). This is not a problem, as the computer, once completed, will
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; have a 60% keyboard, without any of the unusable keys.
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include 'drivers/ps2_keyboard_scancodeset2.asm' ; PS/2 Scan Codeset 2 mappings
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; config (IO port 1)
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PS2KEYB_CLEAR_REG: EQU IO_2
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PS2KEYB_DATA_REG: EQU IO_2 + 1
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PS2KEYB_TRANSMISSION_DURATION: EQU 86 ;@ 100khz ; The time needed for the keyboard to transmit all the 11 bits of data, in CPU clock cycles
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PS2KEYB_BREAK: EQU 0xF0 - %10000000 ; The MSB is dropped: see NOTE on intro above
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; Reads a single character and returns an ascii code when a valid key is pressed. Blocking.
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; @return A The read character
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PS2Keyb_readc:
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in a, (PS2KEYB_DATA_REG) ; reads a character
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add a, 0
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jp z, PS2Keyb_readc ; if char is 0 (NULL), user didn't press any key: wait for character
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; we found something, but it may still be shifting in bits. Allow the keyboard to complete data transmission
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ld a, PS2KEYB_TRANSMISSION_DURATION/5 ; every cycle is 5 CPU cycles
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ps2keyb_readc_waitloop:
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sub 1
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jr nz, ps2keyb_readc_waitloop
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; data transmission should now be complete.
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; check if code is a Break Code. If it is, discard next key as it is a released key
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in a, (PS2KEYB_DATA_REG) ; re-reads the character (it should now be complete)
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ld c, a ; save a, because it will be modified by next compare
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cp PS2KEYB_BREAK ; compare a with Break Code
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jp z, ps2keyb_readc_discard ; if it is a Break Code, jump to discarder routine
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; we read a valid character: clean key registers
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in a, (PS2KEYB_CLEAR_REG)
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; now we will convert keycode in c to ASCII code
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ld hl, PS2KEYB_SCANCODESET_ASCII_MAP ; load start of codeset to ascii map
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ld b, 0 ; reset b, as we are going to do a sum with bc (where c contains the read scancode)
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add hl, bc ; add scancode value to map start addr (we are using it as offset)
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ld a, (hl) ; load the corresponding ascii code in a for return
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ret ; returns in the a register
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ps2keyb_readc_discard:
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; clean key registers
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in a, (PS2KEYB_CLEAR_REG)
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ps2keyb_readc_discard_waitfordata:
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; wait for next non-0 keycode and discards it (it is the code of the released key)
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in a, (PS2KEYB_DATA_REG) ; reads a character
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add a, 0
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jp z, ps2keyb_readc_discard_waitfordata ; if char is 0 (NULL), wait
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; we found something, allow the keyboard to complete data transmission
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ld a, PS2KEYB_TRANSMISSION_DURATION/5 ; every cycle is 5 CPU cycles
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ps2keyb_readc_discard_waitloop:
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sub 1
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jr nz, ps2keyb_readc_discard_waitloop
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; data transmission should now be complete, throw away key code
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in a, (PS2KEYB_CLEAR_REG)
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jp PS2Keyb_readc ; go back and wait for another keycode
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