1368 lines
36 KiB
NASM
1368 lines
36 KiB
NASM
; *******************************************
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; * PAT80 COMPOSITE PAL VIDEO ADAPTER *
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; * Video generator module *
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; *******************************************
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; Implemented following timings in http://blog.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
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; Every line, for 46 times, it loads a byte from memory into PORTA register and then shifts the byte to the left to show another bit (do it 7 times)
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; This also displays byte's MSB pixel "for free", as the video pin is PD7 (last bit of PORTA).
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; This module generates a Composite PAL monochrome signal with a resolution
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; of 416x304 pixels of which only 368x256 pizels are visible (= 46x29 characters).
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; The signal is generated using 16-bit Timer1 and interrupts.
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; How does it work:
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; The screen draw is divided in phases. Every phase does something. I.e. phases 0 to 9
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; represents the first 5 long syncs:
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; (sync goes low, wait 30uS, sync goes high, wait 2uS) x 5 times = 10 phases
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; When the interrupt is called, it uses register r25 (STATUS) to decide what to do.
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;
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; STATUS TABLE:
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; R25 (STATUS): Current status (what the interrupt should do when fired):
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; 0-9 = long sync
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; 10-19 = short sync
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; 20-44 = draw empty lines (top vertical padding)
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; 45 = draw lines (draw 304 lines complete with line sync and back porch, then start short
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; sync: sync pin low and next interrupt after 2uS)
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; 46-70 = draw empty lines (bottom vertical padding)
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; 71-82 = short sync
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; 83-255 = invalid state or screen draw finished: set to 0 and restart from first long sync start
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.equ TIMER_DELAY_60US = 65535 - 1409 ; 719 cycles @ 24Mhz (minus overhead)
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.equ TIMER_DELAY_30US = 65535 - 690 ; 719 cycles @ 24Mhz (minus overhead)
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.equ TIMER_DELAY_2US = 65535 - 17 ; 48 cycles @ 24Mhz (minus overhead)
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.equ TIMER_DELAY_4US = 65535 - 64 ; 96 cycles @ 24Mhz (minus overhead)
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.equ BACK_PORCH_DELAY = 234 ; 186 cycles back porch + 48 cycles to leave 2 chunks empty (image padding)
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; ********* FUNCTIONS CALLED BY INTERRUPT ***********
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on_tim1_ovf:
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; TODO: save BUSY pin status and restore it before RETI, because it could be in BUSY status when interrupted
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; set BUSY pin to indicate the mc is unresponsive from now on
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sbi PORTD, BUSY_PIN
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; called by timer 1 two times per line (every 32 uS) during hsync, unless drawing picture.
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inc STATUS
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; if STATUS >= 152 then STATUS=0
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cpi STATUS, 152 ; TODO: Added a seventh sync pulse at end of screen because at the first short sync after the image, the timer doesn't tick at the right time
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brlo switch_status
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clr STATUS
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; check status and decide what to do
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switch_status:
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cpi STATUS, 10
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brlo long_sync ; 0-9: long sync
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cpi STATUS, 20
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brlo short_sync ; 10-19: short sync
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cpi STATUS, 92
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brlo empty_line ; 20-91: empty lines
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breq start_draw_picture ; 92: draw picture
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cpi STATUS, 140
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brlo empty_line ; 93-139 = draw empty lines
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jmp short_sync ; 140-151 = short sync
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; reti is at end of all previous jumps
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start_draw_picture:
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jmp draw_picture ; the breq instruction can branch only relatively -63 to +64
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long_sync:
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; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz)
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sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
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jmp long_sync_end
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; sync pin is high (sync is not occuring)
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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; set timer in 30uS (reset timer counter)
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ldi r27, high(TIMER_DELAY_30US)
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ldi r26, low(TIMER_DELAY_30US)
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sts TCNT1H,r27
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sts TCNT1L,r26
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; clear BUSY pin to indicate the mc is again responsive from now on
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cbi PORTD, BUSY_PIN
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reti
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long_sync_end:
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; sync pin is low (sync is occuring)
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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; set timer in 2uS:
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ldi r27, high(TIMER_DELAY_2US)
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ldi r26, low(TIMER_DELAY_2US)
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sts TCNT1H,r27
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sts TCNT1L,r26
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; clear BUSY pin to indicate the mc is again responsive from now on
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cbi PORTD, BUSY_PIN
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reti
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short_sync:
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; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz)
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sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
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jmp short_sync_end
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; sync pin is high (sync is not occuring)
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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; set timer in 2uS (reset timer counter)
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ldi r27, high(TIMER_DELAY_2US)
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ldi r26, low(TIMER_DELAY_2US)
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sts TCNT1H,r27
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sts TCNT1L,r26
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; clear BUSY pin to indicate the mc is again responsive from now on
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cbi PORTD, BUSY_PIN
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reti
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short_sync_end:
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; sync pin is low (sync is occuring)
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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; set timer in 30uS:
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ldi r27, high(TIMER_DELAY_30US)
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ldi r26, low(TIMER_DELAY_30US)
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sts TCNT1H,r27
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sts TCNT1L,r26
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; clear BUSY pin to indicate the mc is again responsive from now on
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cbi PORTD, BUSY_PIN
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reti
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empty_line:
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; line sync: 4uS low (96 cycles @ 24Mhz), 60uS high (1440 cycles @ 24Mhz)
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sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
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jmp empty_line_end
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; sync pin is high (sync is not occuring)
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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; set timer in 2uS (reset timer counter)
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ldi r27, high(TIMER_DELAY_4US)
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ldi r26, low(TIMER_DELAY_4US)
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sts TCNT1H,r27
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sts TCNT1L,r26
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; clear BUSY pin to indicate the mc is again responsive from now on
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cbi PORTD, BUSY_PIN
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reti
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empty_line_end:
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; sync pin is low (sync is occuring)
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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; set timer in 30uS:
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ldi r27, high(TIMER_DELAY_60US)
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ldi r26, low(TIMER_DELAY_60US)
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sts TCNT1H,r27
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sts TCNT1L,r26
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; clear BUSY pin to indicate the mc is again responsive from now on
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cbi PORTD, BUSY_PIN
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reti
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draw_picture:
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; save X register
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push XH
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push XL
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; set X register to framebuffer start
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ldi r27, high(FRAMEBUFFER)
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ldi r26, low(FRAMEBUFFER)
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; start 304 picture lines
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ldi LINE_COUNTER, 255 ; line counter
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h_picture_loop:
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; **** start line sync: 4uS, 96 cycles @ 24Mhz
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; video pin goes low before sync
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clr VG_HIGH_ACCUM ; 1 cycle
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out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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ldi VG_HIGH_ACCUM, 31 ; 1 cycle
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l_sync_pulse_loop: ; requires 3 cpu cycles
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dec VG_HIGH_ACCUM ; 1 cycle
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brne l_sync_pulse_loop ; 2 cycle if true, 1 if false
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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; **** end line sync
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; **** start line back porch: 8uS, 192 cycles @ 24Mhz
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; leave time at the end for line setup and draw_line call
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ldi VG_HIGH_ACCUM, BACK_PORCH_DELAY/3 ; 1 cycle
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l_sync_back_porch_loop:
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dec VG_HIGH_ACCUM ; 1 cycle
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brne l_sync_back_porch_loop ; 2 cycle if true, 1 if false
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; **** end back porch
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call draw_line ; 3 cycles (+ 3 to come back to on_line_drawn)
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dec LINE_COUNTER ; decrement line countr ; 1 cycle
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brne h_picture_loop ; if not 0, repeat h_picture_loop ; 2 cycle if true, 1 if false
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; end picture lines
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; restore X register
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pop XL
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pop XH
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; video pin goes low before sync
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clr VG_HIGH_ACCUM ; 1 cycle
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out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle
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; immediately start first end-screen short sync:
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inc STATUS
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jmp short_sync
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; reti is in short_sync
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; end draw_picture
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draw_line:
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; NO loops, as this is time-strict
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; 46 chunks of 8 pixels
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; chunk 1
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ld A, X+ ; load pixel ; 2 cycles
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 2
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ld A, X+ ; load pixel ; 2 cycles
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 3
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ld A, X+ ; load pixel ; 2 cycles
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 4
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ld A, X+ ; load pixel ; 2 cycles
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 5
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ld A, X+ ; load pixel ; 2 cycles
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 6
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ld A, X+ ; load pixel ; 2 cycles
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 7
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ld A, X+ ; load pixel ; 2 cycles
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 8
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ld A, X+ ; load pixel ; 2 cycles
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 9
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ld A, X+ ; load pixel ; 2 cycles
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 10
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ld A, X+ ; load pixel ; 2 cycles
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 11
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ld A, X+ ; load pixel ; 2 cycles
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 12
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ld A, X+ ; load pixel ; 2 cycles
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
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lsr A ; 1 cycle
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out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 13
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 14
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 15
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 16
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 17
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 18
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 19
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 20
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 21
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 22
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 23
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 24
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 25
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 26
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 27
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 28
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 29
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 30
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 31
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 32
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 33
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 34
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 35
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 36
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 37
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 38
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 39
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 40
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 41
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 42
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 43
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 44
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 45
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; chunk 46
|
|
ld A, X+ ; load pixel ; 2 cycles
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
nop ; 1 cycle
|
|
lsr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
|
|
; blank right margin
|
|
clr A ; 1 cycle
|
|
out VIDEO_PORT_OUT, A ; 1 cycle
|
|
ldi VG_HIGH_ACCUM, 28 ; 1 cycle
|
|
eol_porch_loop: ; requires 3 cpu cycles
|
|
dec VG_HIGH_ACCUM ; 1 cycle
|
|
brne eol_porch_loop ; 2 if jumps, 1 if continues
|
|
|
|
ret
|