pato-z80-home-computer/pat80-computer/hardware/schematics/pat80/pat80-cache.lib
2021-03-15 19:30:11 +01:00

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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# CPU_Z80CPU
#
DEF CPU_Z80CPU U 0 40 Y Y 1 F N
F0 "U" -550 1400 50 H V L CNN
F1 "CPU_Z80CPU" 250 1400 50 H V L CNN
F2 "" 0 400 50 H I C CNN
F3 "" 0 400 50 H I C CNN
$FPLIST
DIP*
PDIP*
$ENDFPLIST
DRAW
S -550 1350 550 -1350 0 1 10 f
X A11 1 700 100 150 L 50 50 1 1 O
X D6 10 700 -1100 150 L 50 50 1 1 B
X VCC 11 0 1500 150 D 50 50 1 1 W
X D2 12 700 -700 150 L 50 50 1 1 B
X D7 13 700 -1200 150 L 50 50 1 1 B
X D0 14 700 -500 150 L 50 50 1 1 B
X D1 15 700 -600 150 L 50 50 1 1 B
X ~INT~ 16 -700 500 150 R 50 50 1 1 I
X ~NMI~ 17 -700 600 150 R 50 50 1 1 I
X ~HALT~ 18 -700 -100 150 R 50 50 1 1 O
X ~MREQ~ 19 -700 -700 150 R 50 50 1 1 O
X A12 2 700 0 150 L 50 50 1 1 O
X ~IORQ~ 20 -700 -800 150 R 50 50 1 1 O
X ~RD~ 21 -700 -500 150 R 50 50 1 1 O
X ~WR~ 22 -700 -600 150 R 50 50 1 1 O
X ~BUSACK~ 23 -700 -1200 150 R 50 50 1 1 O
X ~WAIT~ 24 -700 0 150 R 50 50 1 1 I
X ~BUSRQ~ 25 -700 -1100 150 R 50 50 1 1 I
X ~RESET~ 26 -700 1200 150 R 50 50 1 1 I
X ~M1~ 27 -700 200 150 R 50 50 1 1 O
X ~RFSH~ 28 -700 100 150 R 50 50 1 1 O
X GND 29 0 -1500 150 U 50 50 1 1 W
X A13 3 700 -100 150 L 50 50 1 1 O
X A0 30 700 1200 150 L 50 50 1 1 O
X A1 31 700 1100 150 L 50 50 1 1 O
X A2 32 700 1000 150 L 50 50 1 1 O
X A3 33 700 900 150 L 50 50 1 1 O
X A4 34 700 800 150 L 50 50 1 1 O
X A5 35 700 700 150 L 50 50 1 1 O
X A6 36 700 600 150 L 50 50 1 1 O
X A7 37 700 500 150 L 50 50 1 1 O
X A8 38 700 400 150 L 50 50 1 1 O
X A9 39 700 300 150 L 50 50 1 1 O
X A14 4 700 -200 150 L 50 50 1 1 O
X A10 40 700 200 150 L 50 50 1 1 O
X A15 5 700 -300 150 L 50 50 1 1 O
X ~CLK~ 6 -700 900 150 R 50 50 1 1 I C
X D4 7 700 -900 150 L 50 50 1 1 B
X D3 8 700 -800 150 L 50 50 1 1 B
X D5 9 700 -1000 150 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# Memory_EEPROM_28C256
#
DEF Memory_EEPROM_28C256 U 0 20 Y Y 1 F N
F0 "U" -300 1050 50 H V C CNN
F1 "Memory_EEPROM_28C256" 100 -1050 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
DIP*W15.24mm*
SOIC*7.5x17.9mm*P1.27mm*
$ENDFPLIST
DRAW
S -300 1000 300 -1000 1 1 10 f
X A14 1 -400 -500 100 R 50 50 1 1 I
X A0 10 -400 900 100 R 50 50 1 1 I
X D0 11 400 900 100 L 50 50 1 1 T
X D1 12 400 800 100 L 50 50 1 1 T
X D2 13 400 700 100 L 50 50 1 1 T
X GND 14 0 -1100 100 U 50 50 1 1 W
X D3 15 400 600 100 L 50 50 1 1 T
X D4 16 400 500 100 L 50 50 1 1 T
X D5 17 400 400 100 L 50 50 1 1 T
X D6 18 400 300 100 L 50 50 1 1 T
X D7 19 400 200 100 L 50 50 1 1 T
X A12 2 -400 -300 100 R 50 50 1 1 I
X ~CS 20 -400 -900 100 R 50 50 1 1 I
X A10 21 -400 -100 100 R 50 50 1 1 I
X ~OE 22 -400 -800 100 R 50 50 1 1 I
X A11 23 -400 -200 100 R 50 50 1 1 I
X A9 24 -400 0 100 R 50 50 1 1 I
X A8 25 -400 100 100 R 50 50 1 1 I
X A13 26 -400 -400 100 R 50 50 1 1 I
X ~WE 27 -400 -700 100 R 50 50 1 1 I
X VCC 28 0 1100 100 D 50 50 1 1 W
X A7 3 -400 200 100 R 50 50 1 1 I
X A6 4 -400 300 100 R 50 50 1 1 I
X A5 5 -400 400 100 R 50 50 1 1 I
X A4 6 -400 500 100 R 50 50 1 1 I
X A3 7 -400 600 100 R 50 50 1 1 I
X A2 8 -400 700 100 R 50 50 1 1 I
X A1 9 -400 800 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
#End Library