Daniele Verducci (ZenPenguin) faef987494 WIP UART sampling at mid clock		2021-03-15 07:30:36 +01:00
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uart-decoding-logic.circ	WIP UART sampling at mid clock	2021-03-15 07:30:36 +01:00
wip_delay.circ	UART: Thinking how to delay sampling to mid clock	2021-03-06 14:09:38 +01:00