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Merge branch 'master' of ichibi:/home/git/Repositories/pato-z80-home-computer

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This commit is contained in:
Daniele Verducci (ZenPenguin)
2021-01-19 07:40:38 +01:00
parent 90c200e6a9 901fe50fee
commit 03e549a69c
3 changed files with 1299 additions and 337 deletions
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130
pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm
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@@ -17,32 +17,37 @@
; Sync pin: PC0 (pin 22)
; Debug hsync pin: PC1 (pin 23)
;
; RESERVED REGISTERS:
; R25: Current status (what the interrupt should do when fired):
; 0, 1, 2, 3, 4 = long sync
; 5, 6, 7, 8, 9 = short sync
; 10 = draw lines (draw 304 lines complete with line sync and back porch, then start short
; STATUS TABLE:
; R25 (STATUS): Current status (what the interrupt should do when fired):
; 0-9 = long sync
; 10-19 = short sync
; 20 = draw lines (draw 304 lines complete with line sync and back porch, then start short
; sync: sync pin low and next interrupt after 2uS)
; 11, 12, 13, 14, 15, 16 = short sync
; 17-255 = invalid state or screen draw finished: set to 0 and restart from first long sync start
; 21-32 = short sync
; 33-255 = invalid state or screen draw finished: set to 0 and restart from first long sync start
.include "atmega1284definition.asm"
.include "m1284def.inc"
; registers
.def A = r0 ; accumulator
.def STATUS = r25 ; signal status (see STATUS TABLE)
; define constant
.equ SYNC_PIN = PC0 ; Sync pin (pin 22)
.equ DEBUG_PIN = PC1 ; DEBUG: Single vertical sync pulse to trigger oscilloscope (pin 23)
.equ TIMER_DELAY_30US = 65536 - 719 ; 719 cycles @ 24Mhz
.equ TIMER_DELAY_2US = 65536 - 48 ; 48 cycles @ 24Mhz
.equ TIMER_DELAY_30US = 65535 - 690 ; 719 cycles @ 24Mhz (minus overhead)
.equ TIMER_DELAY_2US = 65535 - 17 ; 48 cycles @ 24Mhz (minus overhead)
; memory
.equ FRAMEBUFFER = 0x100
; start vector
.org 0x0000
rjmp main ; jump to main label
.org 0x0012
rjmp on_int1 ; interrupt for timer 1 overflow
rjmp main ; reset vector: jump to main label
.org 0x001E
rjmp on_tim1_ovf ; interrupt for timer 1 overflow
.org 0x40
; main program
main:
; pins setup
@@ -52,7 +57,7 @@ main:
out DDRA, r16 ; set port as output (contains video pin)
;*** Load data into ram ***
; *** Load data into ram ***
; Set X to 0x0100
ldi r27, high(FRAMEBUFFER<<1)
ldi r26, low(FRAMEBUFFER<<1)
@@ -70,11 +75,12 @@ main:
cpi r26, 0b11000000
brne load_mem_loop ; if not 0, repeat h_picture_loop
; timer setup (use 16-bit counter TC1)
; *** timer setup (use 16-bit counter TC1) ***
; The Power Reduction TC1 and TC3 bits in the Power Reduction Registers (PRR0.PRTIM1 and
; PRR1.PRTIM3) must be written to zero to enable the TC1 and TC3 module.
ldi r16, 0b00001000
ldi r16, 0b00000000
sts PRR0, r16
<<<<<<< HEAD
ldi r16, 0b00000001
sts PRR1, r16
; Set TCNT1 (timer counter) to 0xFF00 (the timer will trigger soon)
@@ -94,6 +100,17 @@ main:
; The Global Interrupt Enable bit must be set for the interrupts to be enabled.
ldi r16, 0b10000000
sts SREG, r16
=======
; Set timer prescaler to 1:1
LDI r16,0b00000001
sts TCCR1B,r16
; Enambe timer1 overflow interrupt
LDI r16,0b00000001
STS TIMSK1,r16
; Enable interrupts globally
SEI
; Timer setup completed.
>>>>>>> 901fe50fee42333cc45884e4d9913128272ce175
; loop forever
forever:
@@ -101,24 +118,38 @@ main:
; ********* FUNCTIONS CALLED BY INTERRUPT ***********
on_int1:
; called by timer 1 two times per line (every 32 uS) during hsync. Disabled while drawing picture.
; if r25 >= 32 then r25=0
cpi r25, 32
brlt switch_status
clr r25
on_tim1_ovf:
; debug
; sbi PORTC, DEBUG_PIN ; high
; cbi PORTC, DEBUG_PIN ; low
; ; set timer in 30uS (reset timer counter)
; ldi r27, high(TIMER_DELAY_30US)
; ldi r26, low(TIMER_DELAY_30US)
; sts TCNT1H,r27
; sts TCNT1L,r26
; reti
; debug
; called by timer 1 two times per line (every 32 uS) during hsync, unless drawing picture.
inc STATUS
; if STATUS >= 33 then STATUS=0
cpi STATUS, 35 ; TODO: Added a seventh sync pulse at end of screen because at the first short sync after the image, the timer doesn't tick at the right time
brlo switch_status
clr STATUS
; check status and decide what to do
switch_status:
cpi r25, 5
brlt long_sync ; 0-4: long sync
cpi r25, 10 ; 5-9: short sync
breq draw_picture ; 10: draw picture
jmp short_sync ; 11-16: short_sync
cpi STATUS, 10
brlo long_sync ; 0-9: long sync
cpi STATUS, 20
breq draw_picture ; 20: draw picture
jmp short_sync ; 10-19 or 21-32: short_sync
; reti is at end of all previous jumps
draw_picture:
; increment status
inc r25
; set X register to framebuffer start 0x0100
; (set it a byte before, because it will be incremented at first)
clr r27
@@ -138,7 +169,7 @@ draw_picture:
; video pin goes low before sync
clr r19 ; 1 cycle
out PORTA, r19 ; 1 cycle
cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
ldi r18, 31 ; 1 cycle
l_sync_pulse_loop: ; requires 3 cpu cycles
@@ -201,45 +232,39 @@ draw_picture:
; video pin goes low before sync
clr r19 ; 1 cycle
out PORTA, r19 ; 1 cycle
; debug
; sbi PORTC, DEBUG_PIN ; high
; cbi PORTC, DEBUG_PIN ; low
; debug
; immediately start first end-screen short sync
cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
; set timer in 2uS:
ldi r27, high(TIMER_DELAY_2US<<1)
ldi r26, low(TIMER_DELAY_2US<<1)
sts TCNT1H,r27
sts TCNT1L,r26
reti
; immediately start first end-screen short sync:
inc STATUS
jmp short_sync
; reti is in short_sync
; end draw_picture
long_sync:
; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz)
inc r25 ; increment status counter
sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
jmp long_sync_end
; sync pin is high (sync is not occuring)
cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
; set timer in 30uS (reset timer counter)
ldi r27, high(TIMER_DELAY_30US<<1)
ldi r26, low(TIMER_DELAY_30US<<1)
ldi r27, high(TIMER_DELAY_30US)
ldi r26, low(TIMER_DELAY_30US)
sts TCNT1H,r27
sts TCNT1L,r26
reti
long_sync_end:
; sync pin is low (sync is occuring)
sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
; set timer in 2uS:
ldi r27, high(TIMER_DELAY_2US<<1)
ldi r26, low(TIMER_DELAY_2US<<1)
ldi r27, high(TIMER_DELAY_2US)
ldi r26, low(TIMER_DELAY_2US)
sts TCNT1H,r27
sts TCNT1L,r26
reti
@@ -247,25 +272,24 @@ long_sync:
short_sync:
; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz)
inc r25 ; increment status counter
sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
jmp short_sync_end
; sync pin is high (sync is not occuring)
cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
; set timer in 2uS (reset timer counter)
ldi r27, high(TIMER_DELAY_2US<<1)
ldi r26, low(TIMER_DELAY_2US<<1)
ldi r27, high(TIMER_DELAY_2US)
ldi r26, low(TIMER_DELAY_2US)
sts TCNT1H,r27
sts TCNT1L,r26
reti
short_sync_end:
; sync pin is low (sync is occuring)
sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
; set timer in 30uS:
ldi r27, high(TIMER_DELAY_30US<<1)
ldi r26, low(TIMER_DELAY_30US<<1)
ldi r27, high(TIMER_DELAY_30US)
ldi r26, low(TIMER_DELAY_30US)
sts TCNT1H,r27
sts TCNT1L,r26
reti