Merge branch 'master' of ichibi:/home/git/Repositories/pato-z80-home-computer
This commit is contained in:
Daniele Verducci (ZenPenguin)
commit
03e549a69c
@ -1,284 +0,0 @@
|
|||||||
; ***** CPU REGISTER DEFINITIONS *****************************************
|
|
||||||
.def XH = r27
|
|
||||||
.def XL = r26
|
|
||||||
.def YH = r29
|
|
||||||
.def YL = r28
|
|
||||||
.def ZH = r31
|
|
||||||
.def ZL = r30
|
|
||||||
|
|
||||||
; ***** I/O REGISTER DEFINITIONS *****************************************
|
|
||||||
; NOTE:
|
|
||||||
; Definitions marked "MEMORY MAPPED"are extended I/O ports
|
|
||||||
; and cannot be used with IN/OUT instructions
|
|
||||||
.equ UDR1 = 0xce ; MEMORY MAPPED
|
|
||||||
.equ UBRR1L = 0xcc ; MEMORY MAPPED
|
|
||||||
.equ UBRR1H = 0xcd ; MEMORY MAPPED
|
|
||||||
.equ UCSR1C = 0xca ; MEMORY MAPPED
|
|
||||||
.equ UCSR1B = 0xc9 ; MEMORY MAPPED
|
|
||||||
.equ UCSR1A = 0xc8 ; MEMORY MAPPED
|
|
||||||
.equ UDR0 = 0xc6 ; MEMORY MAPPED
|
|
||||||
.equ UBRR0L = 0xc4 ; MEMORY MAPPED
|
|
||||||
.equ UBRR0H = 0xc5 ; MEMORY MAPPED
|
|
||||||
.equ UCSR0C = 0xc2 ; MEMORY MAPPED
|
|
||||||
.equ UCSR0B = 0xc1 ; MEMORY MAPPED
|
|
||||||
.equ UCSR0A = 0xc0 ; MEMORY MAPPED
|
|
||||||
.equ TWAMR = 0xbd ; MEMORY MAPPED
|
|
||||||
.equ TWCR = 0xbc ; MEMORY MAPPED
|
|
||||||
.equ TWDR = 0xbb ; MEMORY MAPPED
|
|
||||||
.equ TWAR = 0xba ; MEMORY MAPPED
|
|
||||||
.equ TWSR = 0xb9 ; MEMORY MAPPED
|
|
||||||
.equ TWBR = 0xb8 ; MEMORY MAPPED
|
|
||||||
.equ ASSR = 0xb6 ; MEMORY MAPPED
|
|
||||||
.equ OCR2B = 0xb4 ; MEMORY MAPPED
|
|
||||||
.equ OCR2A = 0xb3 ; MEMORY MAPPED
|
|
||||||
.equ TCNT2 = 0xb2 ; MEMORY MAPPED
|
|
||||||
.equ TCCR2B = 0xb1 ; MEMORY MAPPED
|
|
||||||
.equ TCCR2A = 0xb0 ; MEMORY MAPPED
|
|
||||||
.equ OCR3BL = 0x9a ; MEMORY MAPPED
|
|
||||||
.equ OCR3BH = 0x9b ; MEMORY MAPPED
|
|
||||||
.equ OCR3AL = 0x98 ; MEMORY MAPPED
|
|
||||||
.equ OCR3AH = 0x99 ; MEMORY MAPPED
|
|
||||||
.equ ICR3L = 0x96 ; MEMORY MAPPED
|
|
||||||
.equ ICR3H = 0x97 ; MEMORY MAPPED
|
|
||||||
.equ TCNT3L = 0x94 ; MEMORY MAPPED
|
|
||||||
.equ TCNT3H = 0x95 ; MEMORY MAPPED
|
|
||||||
.equ TCCR3C = 0x92 ; MEMORY MAPPED
|
|
||||||
.equ TCCR3B = 0x91 ; MEMORY MAPPED
|
|
||||||
.equ TCCR3A = 0x90 ; MEMORY MAPPED
|
|
||||||
.equ OCR1BL = 0x8a ; MEMORY MAPPED
|
|
||||||
.equ OCR1BH = 0x8b ; MEMORY MAPPED
|
|
||||||
.equ OCR1AL = 0x88 ; MEMORY MAPPED
|
|
||||||
.equ OCR1AH = 0x89 ; MEMORY MAPPED
|
|
||||||
.equ ICR1L = 0x86 ; MEMORY MAPPED
|
|
||||||
.equ ICR1H = 0x87 ; MEMORY MAPPED
|
|
||||||
.equ TCNT1L = 0x84 ; MEMORY MAPPED
|
|
||||||
.equ TCNT1H = 0x85 ; MEMORY MAPPED
|
|
||||||
.equ TCCR1C = 0x82 ; MEMORY MAPPED
|
|
||||||
.equ TCCR1B = 0x81 ; MEMORY MAPPED
|
|
||||||
.equ TCCR1A = 0x80 ; MEMORY MAPPED
|
|
||||||
.equ DIDR1 = 0x7f ; MEMORY MAPPED
|
|
||||||
.equ DIDR0 = 0x7e ; MEMORY MAPPED
|
|
||||||
.equ ADMUX = 0x7c ; MEMORY MAPPED
|
|
||||||
.equ ADCSRB = 0x7b ; MEMORY MAPPED
|
|
||||||
.equ ADCSRA = 0x7a ; MEMORY MAPPED
|
|
||||||
.equ ADCH = 0x79 ; MEMORY MAPPED
|
|
||||||
.equ ADCL = 0x78 ; MEMORY MAPPED
|
|
||||||
.equ PCMSK3 = 0x73 ; MEMORY MAPPED
|
|
||||||
.equ TIMSK3 = 0x71 ; MEMORY MAPPED
|
|
||||||
.equ TIMSK2 = 0x70 ; MEMORY MAPPED
|
|
||||||
.equ TIMSK1 = 0x6f ; MEMORY MAPPED
|
|
||||||
.equ TIMSK0 = 0x6e ; MEMORY MAPPED
|
|
||||||
.equ PCMSK2 = 0x6d ; MEMORY MAPPED
|
|
||||||
.equ PCMSK1 = 0x6c ; MEMORY MAPPED
|
|
||||||
.equ PCMSK0 = 0x6b ; MEMORY MAPPED
|
|
||||||
.equ EICRA = 0x69 ; MEMORY MAPPED
|
|
||||||
.equ PCICR = 0x68 ; MEMORY MAPPED
|
|
||||||
.equ OSCCAL = 0x66 ; MEMORY MAPPED
|
|
||||||
.equ PRR1 = 0x65 ; MEMORY MAPPED
|
|
||||||
.equ PRR0 = 0x64 ; MEMORY MAPPED
|
|
||||||
.equ CLKPR = 0x61 ; MEMORY MAPPED
|
|
||||||
.equ WDTCSR = 0x60 ; MEMORY MAPPED
|
|
||||||
.equ SREG = 0x3f
|
|
||||||
.equ SPL = 0x3d
|
|
||||||
.equ SPH = 0x3e
|
|
||||||
.equ RAMPZ = 0x3b
|
|
||||||
.equ SPMCSR = 0x37
|
|
||||||
.equ MCUCR = 0x35
|
|
||||||
.equ MCUSR = 0x34
|
|
||||||
.equ SMCR = 0x33
|
|
||||||
.equ OCDR = 0x31
|
|
||||||
.equ ACSR = 0x30
|
|
||||||
.equ SPDR = 0x2e
|
|
||||||
.equ SPSR = 0x2d
|
|
||||||
.equ SPCR = 0x2c
|
|
||||||
.equ GPIOR2 = 0x2b
|
|
||||||
.equ GPIOR1 = 0x2a
|
|
||||||
.equ OCR0B = 0x28
|
|
||||||
.equ OCR0A = 0x27
|
|
||||||
.equ TCNT0 = 0x26
|
|
||||||
.equ TCCR0B = 0x25
|
|
||||||
.equ TCCR0A = 0x24
|
|
||||||
.equ GTCCR = 0x23
|
|
||||||
.equ EEARH = 0x22
|
|
||||||
.equ EEARL = 0x21
|
|
||||||
.equ EEDR = 0x20
|
|
||||||
.equ EECR = 0x1f
|
|
||||||
.equ GPIOR0 = 0x1e
|
|
||||||
.equ EIMSK = 0x1d
|
|
||||||
.equ EIFR = 0x1c
|
|
||||||
.equ PCIFR = 0x1b
|
|
||||||
.equ TIFR3 = 0x18
|
|
||||||
.equ TIFR2 = 0x17
|
|
||||||
.equ TIFR1 = 0x16
|
|
||||||
.equ TIFR0 = 0x15
|
|
||||||
.equ PORTD = 0x0b
|
|
||||||
.equ DDRD = 0x0a
|
|
||||||
.equ PIND = 0x09
|
|
||||||
.equ PORTC = 0x08
|
|
||||||
.equ DDRC = 0x07
|
|
||||||
.equ PINC = 0x06
|
|
||||||
.equ PORTB = 0x05
|
|
||||||
.equ DDRB = 0x04
|
|
||||||
.equ PINB = 0x03
|
|
||||||
.equ PORTA = 0x02
|
|
||||||
.equ DDRA = 0x01
|
|
||||||
.equ PINA = 0x00
|
|
||||||
|
|
||||||
; ***** PORTA ************************
|
|
||||||
; PORTA - Port A Data Register
|
|
||||||
.equ PORTA0 = 0 ; Port A Data Register bit 0
|
|
||||||
.equ PA0 = 0 ; For compatibility
|
|
||||||
.equ PORTA1 = 1 ; Port A Data Register bit 1
|
|
||||||
.equ PA1 = 1 ; For compatibility
|
|
||||||
.equ PORTA2 = 2 ; Port A Data Register bit 2
|
|
||||||
.equ PA2 = 2 ; For compatibility
|
|
||||||
.equ PORTA3 = 3 ; Port A Data Register bit 3
|
|
||||||
.equ PA3 = 3 ; For compatibility
|
|
||||||
.equ PORTA4 = 4 ; Port A Data Register bit 4
|
|
||||||
.equ PA4 = 4 ; For compatibility
|
|
||||||
.equ PORTA5 = 5 ; Port A Data Register bit 5
|
|
||||||
.equ PA5 = 5 ; For compatibility
|
|
||||||
.equ PORTA6 = 6 ; Port A Data Register bit 6
|
|
||||||
.equ PA6 = 6 ; For compatibility
|
|
||||||
.equ PORTA7 = 7 ; Port A Data Register bit 7
|
|
||||||
.equ PA7 = 7 ; For compatibility
|
|
||||||
|
|
||||||
; DDRA - Port A Data Direction Register
|
|
||||||
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
|
|
||||||
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
|
|
||||||
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
|
|
||||||
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
|
|
||||||
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
|
|
||||||
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
|
|
||||||
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
|
|
||||||
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
|
|
||||||
|
|
||||||
; PINA - Port A Input Pins
|
|
||||||
.equ PINA0 = 0 ; Input Pins, Port A bit 0
|
|
||||||
.equ PINA1 = 1 ; Input Pins, Port A bit 1
|
|
||||||
.equ PINA2 = 2 ; Input Pins, Port A bit 2
|
|
||||||
.equ PINA3 = 3 ; Input Pins, Port A bit 3
|
|
||||||
.equ PINA4 = 4 ; Input Pins, Port A bit 4
|
|
||||||
.equ PINA5 = 5 ; Input Pins, Port A bit 5
|
|
||||||
.equ PINA6 = 6 ; Input Pins, Port A bit 6
|
|
||||||
.equ PINA7 = 7 ; Input Pins, Port A bit 7
|
|
||||||
|
|
||||||
|
|
||||||
; ***** PORTB ************************
|
|
||||||
; PORTB - Port B Data Register
|
|
||||||
.equ PORTB0 = 0 ; Port B Data Register bit 0
|
|
||||||
.equ PB0 = 0 ; For compatibility
|
|
||||||
.equ PORTB1 = 1 ; Port B Data Register bit 1
|
|
||||||
.equ PB1 = 1 ; For compatibility
|
|
||||||
.equ PORTB2 = 2 ; Port B Data Register bit 2
|
|
||||||
.equ PB2 = 2 ; For compatibility
|
|
||||||
.equ PORTB3 = 3 ; Port B Data Register bit 3
|
|
||||||
.equ PB3 = 3 ; For compatibility
|
|
||||||
.equ PORTB4 = 4 ; Port B Data Register bit 4
|
|
||||||
.equ PB4 = 4 ; For compatibility
|
|
||||||
.equ PORTB5 = 5 ; Port B Data Register bit 5
|
|
||||||
.equ PB5 = 5 ; For compatibility
|
|
||||||
.equ PORTB6 = 6 ; Port B Data Register bit 6
|
|
||||||
.equ PB6 = 6 ; For compatibility
|
|
||||||
.equ PORTB7 = 7 ; Port B Data Register bit 7
|
|
||||||
.equ PB7 = 7 ; For compatibility
|
|
||||||
|
|
||||||
; DDRB - Port B Data Direction Register
|
|
||||||
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
|
|
||||||
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
|
|
||||||
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
|
|
||||||
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
|
|
||||||
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
|
|
||||||
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
|
|
||||||
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
|
|
||||||
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
|
|
||||||
|
|
||||||
; PINB - Port B Input Pins
|
|
||||||
.equ PINB0 = 0 ; Port B Input Pins bit 0
|
|
||||||
.equ PINB1 = 1 ; Port B Input Pins bit 1
|
|
||||||
.equ PINB2 = 2 ; Port B Input Pins bit 2
|
|
||||||
.equ PINB3 = 3 ; Port B Input Pins bit 3
|
|
||||||
.equ PINB4 = 4 ; Port B Input Pins bit 4
|
|
||||||
.equ PINB5 = 5 ; Port B Input Pins bit 5
|
|
||||||
.equ PINB6 = 6 ; Port B Input Pins bit 6
|
|
||||||
.equ PINB7 = 7 ; Port B Input Pins bit 7
|
|
||||||
|
|
||||||
|
|
||||||
; ***** PORTC ************************
|
|
||||||
; PORTC - Port C Data Register
|
|
||||||
.equ PORTC0 = 0 ; Port C Data Register bit 0
|
|
||||||
.equ PC0 = 0 ; For compatibility
|
|
||||||
.equ PORTC1 = 1 ; Port C Data Register bit 1
|
|
||||||
.equ PC1 = 1 ; For compatibility
|
|
||||||
.equ PORTC2 = 2 ; Port C Data Register bit 2
|
|
||||||
.equ PC2 = 2 ; For compatibility
|
|
||||||
.equ PORTC3 = 3 ; Port C Data Register bit 3
|
|
||||||
.equ PC3 = 3 ; For compatibility
|
|
||||||
.equ PORTC4 = 4 ; Port C Data Register bit 4
|
|
||||||
.equ PC4 = 4 ; For compatibility
|
|
||||||
.equ PORTC5 = 5 ; Port C Data Register bit 5
|
|
||||||
.equ PC5 = 5 ; For compatibility
|
|
||||||
.equ PORTC6 = 6 ; Port C Data Register bit 6
|
|
||||||
.equ PC6 = 6 ; For compatibility
|
|
||||||
.equ PORTC7 = 7 ; Port C Data Register bit 7
|
|
||||||
.equ PC7 = 7 ; For compatibility
|
|
||||||
|
|
||||||
; DDRC - Port C Data Direction Register
|
|
||||||
.equ DDC0 = 0 ; Port C Data Direction Register bit 0
|
|
||||||
.equ DDC1 = 1 ; Port C Data Direction Register bit 1
|
|
||||||
.equ DDC2 = 2 ; Port C Data Direction Register bit 2
|
|
||||||
.equ DDC3 = 3 ; Port C Data Direction Register bit 3
|
|
||||||
.equ DDC4 = 4 ; Port C Data Direction Register bit 4
|
|
||||||
.equ DDC5 = 5 ; Port C Data Direction Register bit 5
|
|
||||||
.equ DDC6 = 6 ; Port C Data Direction Register bit 6
|
|
||||||
.equ DDC7 = 7 ; Port C Data Direction Register bit 7
|
|
||||||
|
|
||||||
; PINC - Port C Input Pins
|
|
||||||
.equ PINC0 = 0 ; Port C Input Pins bit 0
|
|
||||||
.equ PINC1 = 1 ; Port C Input Pins bit 1
|
|
||||||
.equ PINC2 = 2 ; Port C Input Pins bit 2
|
|
||||||
.equ PINC3 = 3 ; Port C Input Pins bit 3
|
|
||||||
.equ PINC4 = 4 ; Port C Input Pins bit 4
|
|
||||||
.equ PINC5 = 5 ; Port C Input Pins bit 5
|
|
||||||
.equ PINC6 = 6 ; Port C Input Pins bit 6
|
|
||||||
.equ PINC7 = 7 ; Port C Input Pins bit 7
|
|
||||||
|
|
||||||
|
|
||||||
; ***** PORTD ************************
|
|
||||||
; PORTD - Port D Data Register
|
|
||||||
.equ PORTD0 = 0 ; Port D Data Register bit 0
|
|
||||||
.equ PD0 = 0 ; For compatibility
|
|
||||||
.equ PORTD1 = 1 ; Port D Data Register bit 1
|
|
||||||
.equ PD1 = 1 ; For compatibility
|
|
||||||
.equ PORTD2 = 2 ; Port D Data Register bit 2
|
|
||||||
.equ PD2 = 2 ; For compatibility
|
|
||||||
.equ PORTD3 = 3 ; Port D Data Register bit 3
|
|
||||||
.equ PD3 = 3 ; For compatibility
|
|
||||||
.equ PORTD4 = 4 ; Port D Data Register bit 4
|
|
||||||
.equ PD4 = 4 ; For compatibility
|
|
||||||
.equ PORTD5 = 5 ; Port D Data Register bit 5
|
|
||||||
.equ PD5 = 5 ; For compatibility
|
|
||||||
.equ PORTD6 = 6 ; Port D Data Register bit 6
|
|
||||||
.equ PD6 = 6 ; For compatibility
|
|
||||||
.equ PORTD7 = 7 ; Port D Data Register bit 7
|
|
||||||
.equ PD7 = 7 ; For compatibility
|
|
||||||
|
|
||||||
; DDRD - Port D Data Direction Register
|
|
||||||
.equ DDD0 = 0 ; Port D Data Direction Register bit 0
|
|
||||||
.equ DDD1 = 1 ; Port D Data Direction Register bit 1
|
|
||||||
.equ DDD2 = 2 ; Port D Data Direction Register bit 2
|
|
||||||
.equ DDD3 = 3 ; Port D Data Direction Register bit 3
|
|
||||||
.equ DDD4 = 4 ; Port D Data Direction Register bit 4
|
|
||||||
.equ DDD5 = 5 ; Port D Data Direction Register bit 5
|
|
||||||
.equ DDD6 = 6 ; Port D Data Direction Register bit 6
|
|
||||||
.equ DDD7 = 7 ; Port D Data Direction Register bit 7
|
|
||||||
|
|
||||||
; PIND - Port D Input Pins
|
|
||||||
.equ PIND0 = 0 ; Port D Input Pins bit 0
|
|
||||||
.equ PIND1 = 1 ; Port D Input Pins bit 1
|
|
||||||
.equ PIND2 = 2 ; Port D Input Pins bit 2
|
|
||||||
.equ PIND3 = 3 ; Port D Input Pins bit 3
|
|
||||||
.equ PIND4 = 4 ; Port D Input Pins bit 4
|
|
||||||
.equ PIND5 = 5 ; Port D Input Pins bit 5
|
|
||||||
.equ PIND6 = 6 ; Port D Input Pins bit 6
|
|
||||||
.equ PIND7 = 7 ; Port D Input Pins bit 7
|
|
||||||
1222
pat80-io-devices/composite-pal-adapter/software/avr-assembly/m1284def.inc
Executable file
1222
pat80-io-devices/composite-pal-adapter/software/avr-assembly/m1284def.inc
Executable file
File diff suppressed because it is too large
Load Diff
@ -17,32 +17,37 @@
|
|||||||
; Sync pin: PC0 (pin 22)
|
; Sync pin: PC0 (pin 22)
|
||||||
; Debug hsync pin: PC1 (pin 23)
|
; Debug hsync pin: PC1 (pin 23)
|
||||||
;
|
;
|
||||||
; RESERVED REGISTERS:
|
; STATUS TABLE:
|
||||||
; R25: Current status (what the interrupt should do when fired):
|
; R25 (STATUS): Current status (what the interrupt should do when fired):
|
||||||
; 0, 1, 2, 3, 4 = long sync
|
; 0-9 = long sync
|
||||||
; 5, 6, 7, 8, 9 = short sync
|
; 10-19 = short sync
|
||||||
; 10 = draw lines (draw 304 lines complete with line sync and back porch, then start short
|
; 20 = draw lines (draw 304 lines complete with line sync and back porch, then start short
|
||||||
; sync: sync pin low and next interrupt after 2uS)
|
; sync: sync pin low and next interrupt after 2uS)
|
||||||
; 11, 12, 13, 14, 15, 16 = short sync
|
; 21-32 = short sync
|
||||||
; 17-255 = invalid state or screen draw finished: set to 0 and restart from first long sync start
|
; 33-255 = invalid state or screen draw finished: set to 0 and restart from first long sync start
|
||||||
|
|
||||||
.include "atmega1284definition.asm"
|
.include "m1284def.inc"
|
||||||
|
|
||||||
|
; registers
|
||||||
|
.def A = r0 ; accumulator
|
||||||
|
.def STATUS = r25 ; signal status (see STATUS TABLE)
|
||||||
|
|
||||||
; define constant
|
; define constant
|
||||||
.equ SYNC_PIN = PC0 ; Sync pin (pin 22)
|
.equ SYNC_PIN = PC0 ; Sync pin (pin 22)
|
||||||
.equ DEBUG_PIN = PC1 ; DEBUG: Single vertical sync pulse to trigger oscilloscope (pin 23)
|
.equ DEBUG_PIN = PC1 ; DEBUG: Single vertical sync pulse to trigger oscilloscope (pin 23)
|
||||||
.equ TIMER_DELAY_30US = 65536 - 719 ; 719 cycles @ 24Mhz
|
.equ TIMER_DELAY_30US = 65535 - 690 ; 719 cycles @ 24Mhz (minus overhead)
|
||||||
.equ TIMER_DELAY_2US = 65536 - 48 ; 48 cycles @ 24Mhz
|
.equ TIMER_DELAY_2US = 65535 - 17 ; 48 cycles @ 24Mhz (minus overhead)
|
||||||
|
|
||||||
; memory
|
; memory
|
||||||
.equ FRAMEBUFFER = 0x100
|
.equ FRAMEBUFFER = 0x100
|
||||||
|
|
||||||
; start vector
|
; start vector
|
||||||
.org 0x0000
|
.org 0x0000
|
||||||
rjmp main ; jump to main label
|
rjmp main ; reset vector: jump to main label
|
||||||
.org 0x0012
|
.org 0x001E
|
||||||
rjmp on_int1 ; interrupt for timer 1 overflow
|
rjmp on_tim1_ovf ; interrupt for timer 1 overflow
|
||||||
|
|
||||||
|
.org 0x40
|
||||||
; main program
|
; main program
|
||||||
main:
|
main:
|
||||||
; pins setup
|
; pins setup
|
||||||
@ -52,7 +57,7 @@ main:
|
|||||||
out DDRA, r16 ; set port as output (contains video pin)
|
out DDRA, r16 ; set port as output (contains video pin)
|
||||||
|
|
||||||
|
|
||||||
;*** Load data into ram ***
|
; *** Load data into ram ***
|
||||||
; Set X to 0x0100
|
; Set X to 0x0100
|
||||||
ldi r27, high(FRAMEBUFFER<<1)
|
ldi r27, high(FRAMEBUFFER<<1)
|
||||||
ldi r26, low(FRAMEBUFFER<<1)
|
ldi r26, low(FRAMEBUFFER<<1)
|
||||||
@ -70,11 +75,12 @@ main:
|
|||||||
cpi r26, 0b11000000
|
cpi r26, 0b11000000
|
||||||
brne load_mem_loop ; if not 0, repeat h_picture_loop
|
brne load_mem_loop ; if not 0, repeat h_picture_loop
|
||||||
|
|
||||||
; timer setup (use 16-bit counter TC1)
|
; *** timer setup (use 16-bit counter TC1) ***
|
||||||
; The Power Reduction TC1 and TC3 bits in the Power Reduction Registers (PRR0.PRTIM1 and
|
; The Power Reduction TC1 and TC3 bits in the Power Reduction Registers (PRR0.PRTIM1 and
|
||||||
; PRR1.PRTIM3) must be written to zero to enable the TC1 and TC3 module.
|
; PRR1.PRTIM3) must be written to zero to enable the TC1 and TC3 module.
|
||||||
ldi r16, 0b00001000
|
ldi r16, 0b00000000
|
||||||
sts PRR0, r16
|
sts PRR0, r16
|
||||||
|
<<<<<<< HEAD
|
||||||
ldi r16, 0b00000001
|
ldi r16, 0b00000001
|
||||||
sts PRR1, r16
|
sts PRR1, r16
|
||||||
; Set TCNT1 (timer counter) to 0xFF00 (the timer will trigger soon)
|
; Set TCNT1 (timer counter) to 0xFF00 (the timer will trigger soon)
|
||||||
@ -94,6 +100,17 @@ main:
|
|||||||
; The Global Interrupt Enable bit must be set for the interrupts to be enabled.
|
; The Global Interrupt Enable bit must be set for the interrupts to be enabled.
|
||||||
ldi r16, 0b10000000
|
ldi r16, 0b10000000
|
||||||
sts SREG, r16
|
sts SREG, r16
|
||||||
|
=======
|
||||||
|
; Set timer prescaler to 1:1
|
||||||
|
LDI r16,0b00000001
|
||||||
|
sts TCCR1B,r16
|
||||||
|
; Enambe timer1 overflow interrupt
|
||||||
|
LDI r16,0b00000001
|
||||||
|
STS TIMSK1,r16
|
||||||
|
; Enable interrupts globally
|
||||||
|
SEI
|
||||||
|
; Timer setup completed.
|
||||||
|
>>>>>>> 901fe50fee42333cc45884e4d9913128272ce175
|
||||||
|
|
||||||
; loop forever
|
; loop forever
|
||||||
forever:
|
forever:
|
||||||
@ -101,24 +118,38 @@ main:
|
|||||||
|
|
||||||
|
|
||||||
; ********* FUNCTIONS CALLED BY INTERRUPT ***********
|
; ********* FUNCTIONS CALLED BY INTERRUPT ***********
|
||||||
on_int1:
|
on_tim1_ovf:
|
||||||
; called by timer 1 two times per line (every 32 uS) during hsync. Disabled while drawing picture.
|
; debug
|
||||||
|
; sbi PORTC, DEBUG_PIN ; high
|
||||||
|
; cbi PORTC, DEBUG_PIN ; low
|
||||||
|
; ; set timer in 30uS (reset timer counter)
|
||||||
|
; ldi r27, high(TIMER_DELAY_30US)
|
||||||
|
; ldi r26, low(TIMER_DELAY_30US)
|
||||||
|
; sts TCNT1H,r27
|
||||||
|
; sts TCNT1L,r26
|
||||||
|
; reti
|
||||||
|
; debug
|
||||||
|
|
||||||
; if r25 >= 32 then r25=0
|
|
||||||
cpi r25, 32
|
|
||||||
brlt switch_status
|
|
||||||
clr r25
|
|
||||||
|
; called by timer 1 two times per line (every 32 uS) during hsync, unless drawing picture.
|
||||||
|
inc STATUS
|
||||||
|
; if STATUS >= 33 then STATUS=0
|
||||||
|
cpi STATUS, 35 ; TODO: Added a seventh sync pulse at end of screen because at the first short sync after the image, the timer doesn't tick at the right time
|
||||||
|
brlo switch_status
|
||||||
|
clr STATUS
|
||||||
; check status and decide what to do
|
; check status and decide what to do
|
||||||
switch_status:
|
switch_status:
|
||||||
cpi r25, 5
|
cpi STATUS, 10
|
||||||
brlt long_sync ; 0-4: long sync
|
brlo long_sync ; 0-9: long sync
|
||||||
cpi r25, 10 ; 5-9: short sync
|
cpi STATUS, 20
|
||||||
breq draw_picture ; 10: draw picture
|
breq draw_picture ; 20: draw picture
|
||||||
jmp short_sync ; 11-16: short_sync
|
jmp short_sync ; 10-19 or 21-32: short_sync
|
||||||
|
; reti is at end of all previous jumps
|
||||||
|
|
||||||
draw_picture:
|
draw_picture:
|
||||||
; increment status
|
|
||||||
inc r25
|
|
||||||
; set X register to framebuffer start 0x0100
|
; set X register to framebuffer start 0x0100
|
||||||
; (set it a byte before, because it will be incremented at first)
|
; (set it a byte before, because it will be incremented at first)
|
||||||
clr r27
|
clr r27
|
||||||
@ -208,28 +239,22 @@ draw_picture:
|
|||||||
; debug
|
; debug
|
||||||
|
|
||||||
|
|
||||||
; immediately start first end-screen short sync
|
; immediately start first end-screen short sync:
|
||||||
cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
|
inc STATUS
|
||||||
; set timer in 2uS:
|
jmp short_sync
|
||||||
ldi r27, high(TIMER_DELAY_2US<<1)
|
; reti is in short_sync
|
||||||
ldi r26, low(TIMER_DELAY_2US<<1)
|
|
||||||
sts TCNT1H,r27
|
|
||||||
sts TCNT1L,r26
|
|
||||||
|
|
||||||
reti
|
|
||||||
; end draw_picture
|
; end draw_picture
|
||||||
|
|
||||||
long_sync:
|
long_sync:
|
||||||
; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz)
|
; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz)
|
||||||
inc r25 ; increment status counter
|
|
||||||
|
|
||||||
sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
|
sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
|
||||||
jmp long_sync_end
|
jmp long_sync_end
|
||||||
; sync pin is high (sync is not occuring)
|
; sync pin is high (sync is not occuring)
|
||||||
cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
|
cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
|
||||||
; set timer in 30uS (reset timer counter)
|
; set timer in 30uS (reset timer counter)
|
||||||
ldi r27, high(TIMER_DELAY_30US<<1)
|
ldi r27, high(TIMER_DELAY_30US)
|
||||||
ldi r26, low(TIMER_DELAY_30US<<1)
|
ldi r26, low(TIMER_DELAY_30US)
|
||||||
sts TCNT1H,r27
|
sts TCNT1H,r27
|
||||||
sts TCNT1L,r26
|
sts TCNT1L,r26
|
||||||
reti
|
reti
|
||||||
@ -238,8 +263,8 @@ long_sync:
|
|||||||
; sync pin is low (sync is occuring)
|
; sync pin is low (sync is occuring)
|
||||||
sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
|
sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
|
||||||
; set timer in 2uS:
|
; set timer in 2uS:
|
||||||
ldi r27, high(TIMER_DELAY_2US<<1)
|
ldi r27, high(TIMER_DELAY_2US)
|
||||||
ldi r26, low(TIMER_DELAY_2US<<1)
|
ldi r26, low(TIMER_DELAY_2US)
|
||||||
sts TCNT1H,r27
|
sts TCNT1H,r27
|
||||||
sts TCNT1L,r26
|
sts TCNT1L,r26
|
||||||
reti
|
reti
|
||||||
@ -247,15 +272,14 @@ long_sync:
|
|||||||
|
|
||||||
short_sync:
|
short_sync:
|
||||||
; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz)
|
; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz)
|
||||||
inc r25 ; increment status counter
|
|
||||||
|
|
||||||
sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
|
sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
|
||||||
jmp short_sync_end
|
jmp short_sync_end
|
||||||
; sync pin is high (sync is not occuring)
|
; sync pin is high (sync is not occuring)
|
||||||
cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
|
cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
|
||||||
; set timer in 2uS (reset timer counter)
|
; set timer in 2uS (reset timer counter)
|
||||||
ldi r27, high(TIMER_DELAY_2US<<1)
|
ldi r27, high(TIMER_DELAY_2US)
|
||||||
ldi r26, low(TIMER_DELAY_2US<<1)
|
ldi r26, low(TIMER_DELAY_2US)
|
||||||
sts TCNT1H,r27
|
sts TCNT1H,r27
|
||||||
sts TCNT1L,r26
|
sts TCNT1L,r26
|
||||||
reti
|
reti
|
||||||
@ -264,8 +288,8 @@ short_sync:
|
|||||||
; sync pin is low (sync is occuring)
|
; sync pin is low (sync is occuring)
|
||||||
sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
|
sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
|
||||||
; set timer in 30uS:
|
; set timer in 30uS:
|
||||||
ldi r27, high(TIMER_DELAY_30US<<1)
|
ldi r27, high(TIMER_DELAY_30US)
|
||||||
ldi r26, low(TIMER_DELAY_30US<<1)
|
ldi r26, low(TIMER_DELAY_30US)
|
||||||
sts TCNT1H,r27
|
sts TCNT1H,r27
|
||||||
sts TCNT1L,r26
|
sts TCNT1L,r26
|
||||||
reti
|
reti
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user