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Copying data bus to framebuffer memory, but ignoring clock signal

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Daniele Verducci su MatissePenguin
2021-01-19 20:55:11 +01:00
parent 792db80ab4
commit 17fdf97f75
2 changed files with 38 additions and 4 deletions
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22
pat80-io-devices/composite-pal-adapter/software/avr-assembly/communication.asm
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@@ -5,3 +5,25 @@
; This module manages the communication between Pat80 and
; the video adapter.
; The data port is PORTB. The CLK (clock) signal is on PORTD0
; and the RS (register select) on PORTD1
; Initializes and waits for a byte on PORTB
comm_init:
; Set Z to framebuffer start
ldi r31, high(FRAMEBUFFER<<1)
ldi r30, low(FRAMEBUFFER<<1)
comm_wait_byte:
in r24, PINB ; read PORTB
; Check continuously CLK until a LOW is found
sbic PORTD, CLK_PIN
jmp comm_wait_byte
; CLK triggered: Copy PORTB to the next framebuffer byte
st Z+, r24
; if reached the last framebuffer byte, exit cycle
cpi r31, 0b00111110
brne comm_wait_byte ; if not 0, repeat h_picture_loop
cpi r30, 0b11000000
brne comm_wait_byte ; if not 0, repeat h_picture_loop
jmp comm_init ; filled all memory: reset framebuffer position