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Copying data bus to framebuffer memory, but ignoring clock signal

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Daniele Verducci su MatissePenguin 2021-01-19 20:55:11 +01:00
parent 792db80ab4
commit 17fdf97f75
2 changed files with 38 additions and 4 deletions
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22
pat80-io-devices/composite-pal-adapter/software/avr-assembly/communication.asm
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@ -5,3 +5,25 @@
; This module manages the communication between Pat80 and ; This module manages the communication between Pat80 and
; the video adapter. ; the video adapter.
; The data port is PORTB. The CLK (clock) signal is on PORTD0
; and the RS (register select) on PORTD1
; Initializes and waits for a byte on PORTB
comm_init:
; Set Z to framebuffer start
ldi r31, high(FRAMEBUFFER<<1)
ldi r30, low(FRAMEBUFFER<<1)
comm_wait_byte:
in r24, PINB ; read PORTB
; Check continuously CLK until a LOW is found
sbic PORTD, CLK_PIN
jmp comm_wait_byte
; CLK triggered: Copy PORTB to the next framebuffer byte
st Z+, r24
; if reached the last framebuffer byte, exit cycle
cpi r31, 0b00111110
brne comm_wait_byte ; if not 0, repeat h_picture_loop
cpi r30, 0b11000000
brne comm_wait_byte ; if not 0, repeat h_picture_loop
jmp comm_init ; filled all memory: reset framebuffer position

20
pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm
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@ -19,9 +19,6 @@
; ;
.include "m1284def.inc" ; Atmega 1280 device definition .include "m1284def.inc" ; Atmega 1280 device definition
.include "video_generator.asm" ; Asyncronous timer-interrupt-based video generation
.include "character_generator.asm" ; Character generator
.include "communication.asm" ; Communication with Pat80
; reserved registers ; reserved registers
.def A = r0 ; accumulator .def A = r0 ; accumulator
@ -30,6 +27,7 @@
; define constant ; define constant
.equ SYNC_PIN = PC0 ; Sync pin (pin 22) .equ SYNC_PIN = PC0 ; Sync pin (pin 22)
.equ DEBUG_PIN = PC1 ; DEBUG: Single vertical sync pulse to trigger oscilloscope (pin 23) .equ DEBUG_PIN = PC1 ; DEBUG: Single vertical sync pulse to trigger oscilloscope (pin 23)
.equ CLK_PIN = PD7
; memory ; memory
.equ FRAMEBUFFER = 0x100 .equ FRAMEBUFFER = 0x100
@ -46,8 +44,13 @@ main:
; pins setup ; pins setup
sbi DDRC, SYNC_PIN ; set pin as output sbi DDRC, SYNC_PIN ; set pin as output
sbi DDRC, DEBUG_PIN ; set pin as output sbi DDRC, DEBUG_PIN ; set pin as output
cbi DDRD, CLK_PIN ; set pin as input
ldi r16, 0xFF ldi r16, 0xFF
out DDRA, r16 ; set port as output (contains video pin) out DDRA, r16 ; set port as output (contains video pin)
ldi r16, 0x00
out DDRB, r16 ; set port as input (used as data bus)
; *** timer setup (use 16-bit counter TC1) *** ; *** timer setup (use 16-bit counter TC1) ***
; The Power Reduction TC1 and TC3 bits in the Power Reduction Registers (PRR0.PRTIM1 and ; The Power Reduction TC1 and TC3 bits in the Power Reduction Registers (PRR0.PRTIM1 and
@ -64,6 +67,15 @@ main:
SEI SEI
; Timer setup completed. ; Timer setup completed.
; loop forever ; Wait for data (it never exits)
jmp comm_init
forever: forever:
jmp forever jmp forever
.include "video_generator.asm" ; Asyncronous timer-interrupt-based video generation
.include "character_generator.asm" ; Character generator
.include "communication.asm" ; Communication with Pat80