penguin86/pato-z80-home-computer
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First working image with a lot of jitter

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This commit is contained in:
Daniele Verducci su MatissePenguin 2021-01-02 20:43:42 +01:00
parent 60243dc95f
commit 7e1facf59f
1 changed files with 63 additions and 2 deletions
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65
pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm
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@ -18,11 +18,19 @@ main:
v_refresh_loop: v_refresh_loop:
; start 5 long sync pulses ; start 5 long sync pulses
call long_sync
call long_sync
call long_sync
call long_sync
call long_sync
; end 5 long sync pulses ; end 5 long sync pulses
; start 5 short sync pulses ; start 5 short sync pulses
call short_sync
call short_sync
call short_sync
call short_sync
call short_sync
; end 5 short sync pulses ; end 5 short sync pulses
; start 304 picture lines ; start 304 picture lines
@ -79,3 +87,56 @@ v_refresh_loop:
dec r16 ; decrement outside counter dec r16 ; decrement outside counter
brne h_picture_outer_loop ; if not 0, repeat h_picture_loop brne h_picture_outer_loop ; if not 0, repeat h_picture_loop
; end picture lines ; end picture lines
; start 6 short sync pulses
call short_sync
call short_sync
call short_sync
call short_sync
call short_sync
; end 6 short sync pulses
jmp v_refresh_loop
; end vertical refresh
long_sync:
; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz)
cbi PORTD, SYNC_PIN ; sync goes low (0v) ; 2 cycle
ldi r18, 120 ; 1 cycle
long_sync_low_loop: ; requires 6 cpu cycles
nop ; 1 cycle
nop ; 1 cycle
nop ; 1 cycle
dec r18 ; 1 cycle
brne long_sync_low_loop ; 2 cycle if true, 1 if false
sbi PORTD, SYNC_PIN ; sync goes high (0.3v)
ldi r18, 16 ; 1 cycle
long_sync_high_loop: ; requires 3 cpu cycles
dec r18 ; 1 cycle
brne long_sync_high_loop ; 2 cycle if true, 1 if false
ret
short_sync:
; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high
cbi PORTD, SYNC_PIN ; sync goes low (0v) ; 2 cycle
ldi r18, 16 ; 1 cycle
short_sync_low_loop: ; requires 3 cpu cycles
dec r18 ; 1 cycle
brne long_sync_low_loop ; 2 cycle if true, 1 if false
sbi PORTD, SYNC_PIN ; sync goes high (0.3v)
ldi r18, 120 ; 1 cycle
short_sync_high_loop: ; requires 6 cpu cycles
nop ; 1 cycle
nop ; 1 cycle
nop ; 1 cycle
dec r18 ; 1 cycle
brne short_sync_high_loop ; 2 cycle if true, 1 if false
ret