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pato-z80-home-computer/pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm

1480 lines
35 KiB
NASM
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Horyzontal timings (working, checked with oscilloscope)
2021-01-02 19:54:17 +01:00
; VIDEO COMPOSITE PAL IO DEVICE
; Implemented following timings in http://blog.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
Read framebuffer from mc's memory
2021-01-07 13:32:01 +01:00
; Every line, for 52 times, it loads a byte from memory into PORTD register and then shifts the byte to the left to show another bit (do it 7 times)
; This also displays byte's MSB pixel "for free", as the video pin is PD7 (last bit of PORTD).
Horyzontal timings (working, checked with oscilloscope)
2021-01-02 19:54:17 +01:00
Reorganized folders, added pal-adapter io device folder
2021-01-02 16:33:51 +01:00
.include "atmega1284definition.asm"
; define constant
Loses sync when loading from memory
2021-01-06 00:19:15 +01:00
.equ SYNC_PIN = PC0 ; Sync pin (pin 22)
.equ VIDEO_PIN = PD7 ; Video pin (pin 21)
.equ DEBUG_PIN = PC1 ; DEBUG: Single vertical sync pulse to trigger oscilloscope (pin 23)
; memory
.equ FRAMEBUFFER = 0x100
Reorganized folders, added pal-adapter io device folder
2021-01-02 16:33:51 +01:00
; start vector
.org 0x0000
rjmp main ; jump to main label
; main program
main:
Loses sync when loading from memory
2021-01-06 00:19:15 +01:00
sbi DDRC, SYNC_PIN ; set pin as output
sbi DDRC, DEBUG_PIN ; set pin as output
ldi r16, 0xFF
out DDRD, r16 ; set port as output
Read framebuffer from mc's memory
2021-01-07 13:32:01 +01:00
WIP fucking video generation
2021-01-07 09:14:09 +01:00
;*** Load data into ram ***
Read framebuffer from mc's memory
2021-01-07 13:32:01 +01:00
; Set X to 0x0100
ldi r27, 0x01
clr r26
ldi r16, 0xFF ; counter
WIP fucking video generation
2021-01-07 09:14:09 +01:00
load_mem_loop:
Read framebuffer from mc's memory
2021-01-07 13:32:01 +01:00
;mov r17, r26 ; use XL as memory content (TODO replace with real content)
ldi r17, 0b10101010
st X+, r17
WIP fucking video generation
2021-01-07 09:14:09 +01:00
dec r16 ; decrement outside counter
brne load_mem_loop ; if not 0, repeat h_picture_loop
Horyzontal timings (working, checked with oscilloscope)
2021-01-02 19:54:17 +01:00
v_refresh_loop:
Read framebuffer from mc's memory
2021-01-07 13:32:01 +01:00
; set X register to framebuffer start 0x0100
ldi r27, 0x01
clr r26
Loses sync when loading from memory
2021-01-06 00:19:15 +01:00
Horyzontal timings (working, checked with oscilloscope)
2021-01-02 19:54:17 +01:00
; start 5 long sync pulses
First working image with a lot of jitter
2021-01-02 20:43:42 +01:00
call long_sync
call long_sync
call long_sync
call long_sync
call long_sync
Horyzontal timings (working, checked with oscilloscope)
2021-01-02 19:54:17 +01:00
; end 5 long sync pulses
; start 5 short sync pulses
First working image with a lot of jitter
2021-01-02 20:43:42 +01:00
call short_sync
call short_sync
call short_sync
call short_sync
call short_sync
Horyzontal timings (working, checked with oscilloscope)
2021-01-02 19:54:17 +01:00
; end 5 short sync pulses
; start 304 picture lines
ldi r16, 2
h_picture_outer_loop:
ldi r17, 152 ; line counter
h_picture_loop:
Read framebuffer from mc's memory
2021-01-07 13:32:01 +01:00
; debug
; sbi PORTC, DEBUG_PIN ; high
; cbi PORTC, DEBUG_PIN ; low
; debug
Horyzontal timings (working, checked with oscilloscope)
2021-01-02 19:54:17 +01:00
Read framebuffer from mc's memory
2021-01-07 13:32:01 +01:00
; **** start line sync: 4uS, 96 cycles @ 24Mhz
cbi PORTD, VIDEO_PIN ; video pin goes low before sync ; 2 cycles
cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
ldi r18, 31 ; 1 cycle
l_sync_pulse_loop: ; requires 3 cpu cycles
dec r18 ; 1 cycle
brne l_sync_pulse_loop ; 2 cycle if true, 1 if false
sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
; **** end line sync
; **** start line back porch: 8uS, 192 cycles @ 24Mhz
; leave time at the end for line setup and draw_line call
ldi r18, 62 ; 1 cycle
l_sync_back_porch_loop:
dec r18 ; 1 cycle
brne l_sync_back_porch_loop ; 2 cycle if true, 1 if false
; **** end back porch
jmp draw_line ; 3 cycles (+ 3 to come back to on_line_drawn)
; **** draws line pixels: 52uS, 1248 cycles @ 24Mhz ****
on_line_drawn:
; debug
; sbi PORTC, DEBUG_PIN ; high
; cbi PORTC, DEBUG_PIN ; low
; debug
dec r17 ; decrement line countr ; 1 cycle
brne h_picture_loop ; if not 0, repeat h_picture_loop ; 2 cycle if true, 1 if false
dec r16 ; decrement outside counter ; 1 cycle
brne h_picture_outer_loop ; if not 0, repeat h_picture_loop ; 2 cycle if true, 1 if false
Horyzontal timings (working, checked with oscilloscope)
2021-01-02 19:54:17 +01:00
; end picture lines
First working image with a lot of jitter
2021-01-02 20:43:42 +01:00
; start 6 short sync pulses
call short_sync
call short_sync
call short_sync
call short_sync
call short_sync
Fixed timings
2021-01-03 15:30:06 +01:00
call short_sync
First working image with a lot of jitter
2021-01-02 20:43:42 +01:00
; end 6 short sync pulses
Fixed timings
2021-01-03 15:30:06 +01:00
; debug
Read framebuffer from mc's memory
2021-01-07 13:32:01 +01:00
; sbi PORTC, DEBUG_PIN ; high
; cbi PORTC, DEBUG_PIN ; low
Fixed timings
2021-01-03 15:30:06 +01:00
; debug
First working image with a lot of jitter
2021-01-02 20:43:42 +01:00
jmp v_refresh_loop
; end vertical refresh
long_sync:
; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz)
Loses sync when loading from memory
2021-01-06 00:19:15 +01:00
cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
First working image with a lot of jitter
2021-01-02 20:43:42 +01:00
ldi r18, 120 ; 1 cycle
long_sync_low_loop: ; requires 6 cpu cycles
nop ; 1 cycle
nop ; 1 cycle
nop ; 1 cycle
dec r18 ; 1 cycle
brne long_sync_low_loop ; 2 cycle if true, 1 if false
Loses sync when loading from memory
2021-01-06 00:19:15 +01:00
sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
First working image with a lot of jitter
2021-01-02 20:43:42 +01:00
Fixed timings
2021-01-03 15:30:06 +01:00
ldi r18, 15 ; 1 cycle
First working image with a lot of jitter
2021-01-02 20:43:42 +01:00
long_sync_high_loop: ; requires 3 cpu cycles
dec r18 ; 1 cycle
brne long_sync_high_loop ; 2 cycle if true, 1 if false
ret
short_sync:
Fixed timings
2021-01-03 15:30:06 +01:00
; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz)
Loses sync when loading from memory
2021-01-06 00:19:15 +01:00
cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
First working image with a lot of jitter
2021-01-02 20:43:42 +01:00
Fixed timings
2021-01-03 15:30:06 +01:00
ldi r18, 15 ; 1 cycle
First working image with a lot of jitter
2021-01-02 20:43:42 +01:00
short_sync_low_loop: ; requires 3 cpu cycles
dec r18 ; 1 cycle
Fixed timings
2021-01-03 15:30:06 +01:00
brne short_sync_low_loop ; 2 cycle if true, 1 if false
First working image with a lot of jitter
2021-01-02 20:43:42 +01:00
Loses sync when loading from memory
2021-01-06 00:19:15 +01:00
sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
First working image with a lot of jitter
2021-01-02 20:43:42 +01:00
ldi r18, 120 ; 1 cycle
short_sync_high_loop: ; requires 6 cpu cycles
nop ; 1 cycle
nop ; 1 cycle
nop ; 1 cycle
dec r18 ; 1 cycle
brne short_sync_high_loop ; 2 cycle if true, 1 if false
New test pattern, still hsync issues
2021-01-03 12:48:38 +01:00
ret
Read framebuffer from mc's memory
2021-01-07 13:32:01 +01:00
draw_line:
; NO loops, as this is time-strict
; 52 chunks of 8 pixels
; chunk 1
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 2
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 3
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 4
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 5
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 6
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 7
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 8
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 9
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 10
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 11
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 12
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 13
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 14
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 15
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 16
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 17
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 18
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 19
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 20
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 21
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 22
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 23
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 24
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 25
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 26
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 27
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 28
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 29
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 30
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 31
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 32
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 33
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 34
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 35
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 36
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 37
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 38
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 39
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 40
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 41
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 42
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 43
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 44
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 45
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 46
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 47
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 48
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 49
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 50
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 51
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
; chunk 52
ld r19, X+ ; load pixel ; 2 cycles
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
nop ; 1 cycle
lsl r19 ; 1 cycle
out PORTD, r19 ; 1 cycle
New test pattern, still hsync issues
2021-01-03 12:48:38 +01:00
Read framebuffer from mc's memory
2021-01-07 13:32:01 +01:00
; return
jmp on_line_drawn ; 3 cycle
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