Loses sync when loading from memory
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Daniele Verducci su MatissePenguin
parent
09785e1317
commit
06779c5442
@ -4,9 +4,12 @@
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.include "atmega1284definition.asm"
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; define constant
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.equ SYNC_PIN = PD7 ; Sync pin is on Port D 7 (pin 21)
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.equ VIDEO_PIN = PD6 ; Video pin is on Port D 6 (pin 20)
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.equ DEBUG_PIN = PD5 ; Video pin is on Port D 5 (pin 19)
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.equ SYNC_PIN = PC0 ; Sync pin (pin 22)
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.equ VIDEO_PIN = PD7 ; Video pin (pin 21)
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.equ DEBUG_PIN = PC1 ; DEBUG: Single vertical sync pulse to trigger oscilloscope (pin 23)
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; memory
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.equ FRAMEBUFFER = 0x100
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; start vector
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.org 0x0000
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@ -14,11 +17,39 @@
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; main program
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main:
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sbi DDRD, SYNC_PIN ; set pin as output
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sbi DDRD, VIDEO_PIN ; set pin as output
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sbi DDRD, DEBUG_PIN ; set pin as output
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sbi DDRC, SYNC_PIN ; set pin as output
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sbi DDRC, DEBUG_PIN ; set pin as output
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ldi r16, 0xFF
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out DDRD, r16 ; set port as output
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; Load ram addr into register X
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ldi r16,0x00
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mov r0,r16
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ldi r16,0x01
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mov r1,r16
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mov XL,r0
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mov XH,r1
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; DEBUG: loads some static data in ram
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ldi r18, 255
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fill_mem_loop1:
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st X+, r18
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dec r18
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brne fill_mem_loop1
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; END DEBUG
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v_refresh_loop:
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; reset memory position counter
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;ldi XL, 0x00
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;ldi XH, 0x01
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ldi r16,0x00
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mov r0,r16
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ldi r16,0x01
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mov r1,r16
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mov XL,r0
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mov XH,r1
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; start 5 long sync pulses
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call long_sync
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call long_sync
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@ -41,31 +72,42 @@ v_refresh_loop:
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ldi r17, 152 ; line counter
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h_picture_loop:
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call line_sync
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; start image: 52uS, 1247 cycles @ 24Mhz
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; 3 bande da 416 cicli
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; start line pixels: 52uS, 1247 cycles @ 24Mhz
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ldi r18, 52 ; 1 cycle
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l_sync_video_loop: ; 24 cycles
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; Load a byte from memory into PORTD register and increment the counter.
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; This also displays byte's MSB pixel "for free", as the video pin is PD7
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; (last bit of PORTD).
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;ld r19, X+ ; 2 cycles
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ld r19, X ; 1 cycle
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nop
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ldi r18, 59 ; 1 cycle
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l_sync_video_loop1:
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sbi PORTD, VIDEO_PIN ; video goes high ; 2 cycle
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dec r18 ; 1 cycle
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cbi PORTD, VIDEO_PIN ; video goes low ; 2 cycle
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brne l_sync_video_loop1 ; 2 cycle if true, 1 if false
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ldi r18, 137 ; 1 cycle
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l_sync_video_loop2:
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dec r18 ; 1 cycle
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brne l_sync_video_loop2 ; 2 cycle if true, 1 if false
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sbi PORTD, VIDEO_PIN ; video goes high
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ldi r18, 138 ; 1 cycle
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l_sync_video_loop3:
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dec r18 ; 1 cycle
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brne l_sync_video_loop3 ; 2 cycle if true, 1 if false
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cbi PORTD, VIDEO_PIN ; video goes low
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; end image
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out PORTD, r19 ; 1 cycle
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; Shift the byte to the left to show another bit (do it 7 times)
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lsl r19 ; 1 cycle
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out PORTD, r19
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nop
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lsl r19 ; 1 cycle
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out PORTD, r19
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nop
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lsl r19 ; 1 cycle
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out PORTD, r19
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nop
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lsl r19 ; 1 cycle
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out PORTD, r19
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nop
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lsl r19 ; 1 cycle
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out PORTD, r19
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nop
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lsl r19 ; 1 cycle
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out PORTD, r19
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nop ; 1 cycle
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dec r18 ; 1 cycle
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brne l_sync_video_loop ; 2 cycles if jumps (1 if continues)
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; end line pixels
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cbi PORTD, VIDEO_PIN ; video pin goes low before sync
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dec r17 ; decrement line counter
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brne h_picture_loop ; if not 0, repeat h_picture_loop
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@ -83,8 +125,8 @@ v_refresh_loop:
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; end 6 short sync pulses
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; debug
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sbi PORTD, DEBUG_PIN ; high
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cbi PORTD, DEBUG_PIN ; low
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sbi PORTC, DEBUG_PIN ; high
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cbi PORTC, DEBUG_PIN ; low
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; debug
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jmp v_refresh_loop
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@ -92,7 +134,7 @@ v_refresh_loop:
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long_sync:
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; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz)
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cbi PORTD, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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ldi r18, 120 ; 1 cycle
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long_sync_low_loop: ; requires 6 cpu cycles
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@ -102,7 +144,7 @@ long_sync:
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dec r18 ; 1 cycle
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brne long_sync_low_loop ; 2 cycle if true, 1 if false
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sbi PORTD, SYNC_PIN ; sync goes high (0.3v)
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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ldi r18, 15 ; 1 cycle
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long_sync_high_loop: ; requires 3 cpu cycles
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@ -113,14 +155,14 @@ long_sync:
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short_sync:
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; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz)
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cbi PORTD, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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ldi r18, 15 ; 1 cycle
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short_sync_low_loop: ; requires 3 cpu cycles
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dec r18 ; 1 cycle
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brne short_sync_low_loop ; 2 cycle if true, 1 if false
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sbi PORTD, SYNC_PIN ; sync goes high (0.3v)
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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ldi r18, 120 ; 1 cycle
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short_sync_high_loop: ; requires 6 cpu cycles
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@ -135,12 +177,12 @@ short_sync:
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line_sync:
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; line sync & front porch
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; start line sync: 4uS, 96 cycles @ 24Mhz
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cbi PORTD, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
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ldi r18, 32 ; 1 cycle
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l_sync_pulse_loop: ; requires 3 cpu cycles
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dec r18 ; 1 cycle
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brne l_sync_pulse_loop ; 2 cycle if true, 1 if false
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sbi PORTD, SYNC_PIN ; sync goes high (0.3v)
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sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
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; end line sync
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; start back porch: 8uS, 192 cycles @ 24Mhz
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