pato-z80-home-computer/pat80-io-devices/composite-pal-adapter/software/avr-assembly/video_generator.asm

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; *******************************************
; * PAT80 COMPOSITE PAL VIDEO ADAPTER *
; * Video generator module *
; *******************************************
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; Implemented following timings in http://blog.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
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; Every line, for 46 times, it loads a byte from memory into PORTA register and then shifts the byte to the left to show another bit (do it 7 times)
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; This also displays byte's MSB pixel "for free", as the video pin is PD7 (last bit of PORTA).
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; This module generates a Composite PAL monochrome signal with a resolution
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; of 416x304 pixels of which only 368x256 pizels are visible (= 46x29 characters).
; The signal is generated using 16-bit Timer1 and interrupts.
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; How does it work:
; The screen draw is divided in phases. Every phase does something. I.e. phases 0 to 9
; represents the first 5 long syncs:
; (sync goes low, wait 30uS, sync goes high, wait 2uS) x 5 times = 10 phases
; When the interrupt is called, it uses register r25 (STATUS) to decide what to do.
;
; STATUS TABLE:
; R25 (STATUS): Current status (what the interrupt should do when fired):
; 0-9 = long sync
; 10-19 = short sync
; 20-44 = draw empty lines (top vertical padding)
; 45 = draw lines (draw 304 lines complete with line sync and back porch, then start short
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; sync: sync pin low and next interrupt after 2uS)
; 46-70 = draw empty lines (bottom vertical padding)
; 71-82 = short sync
; 83-255 = invalid state or screen draw finished: set to 0 and restart from first long sync start
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.equ TIMER_DELAY_60US = 65535 - 1409 ; 719 cycles @ 24Mhz (minus overhead)
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.equ TIMER_DELAY_30US = 65535 - 690 ; 719 cycles @ 24Mhz (minus overhead)
.equ TIMER_DELAY_2US = 65535 - 17 ; 48 cycles @ 24Mhz (minus overhead)
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.equ TIMER_DELAY_4US = 65535 - 64 ; 96 cycles @ 24Mhz (minus overhead)
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.equ BACK_PORCH_DELAY = 234 ; 186 cycles back porch + 48 cycles to leave 2 chunks empty (image padding)
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; ********* FUNCTIONS CALLED BY INTERRUPT ***********
on_tim1_ovf:
; TODO: save BUSY pin status and restore it before RETI, because it could be in BUSY status when interrupted
; set BUSY pin to indicate the mc is unresponsive from now on
sbi PORTD, BUSY_PIN
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; called by timer 1 two times per line (every 32 uS) during hsync, unless drawing picture.
inc STATUS
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; if STATUS >= 152 then STATUS=0
cpi STATUS, 152 ; TODO: Added a seventh sync pulse at end of screen because at the first short sync after the image, the timer doesn't tick at the right time
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brlo switch_status
clr STATUS
; check status and decide what to do
switch_status:
cpi STATUS, 10
brlo long_sync ; 0-9: long sync
cpi STATUS, 20
brlo short_sync ; 10-19: short sync
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cpi STATUS, 92
brlo empty_line ; 20-91: empty lines
breq start_draw_picture ; 92: draw picture
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cpi STATUS, 140
brlo empty_line ; 93-139 = draw empty lines
jmp short_sync ; 140-151 = short sync
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; reti is at end of all previous jumps
start_draw_picture:
jmp draw_picture ; the breq instruction can branch only relatively -63 to +64
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long_sync:
; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz)
sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
jmp long_sync_end
; sync pin is high (sync is not occuring)
cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
; set timer in 30uS (reset timer counter)
ldi r27, high(TIMER_DELAY_30US)
ldi r26, low(TIMER_DELAY_30US)
sts TCNT1H,r27
sts TCNT1L,r26
; clear BUSY pin to indicate the mc is again responsive from now on
cbi PORTD, BUSY_PIN
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reti
long_sync_end:
; sync pin is low (sync is occuring)
sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
; set timer in 2uS:
ldi r27, high(TIMER_DELAY_2US)
ldi r26, low(TIMER_DELAY_2US)
sts TCNT1H,r27
sts TCNT1L,r26
; clear BUSY pin to indicate the mc is again responsive from now on
cbi PORTD, BUSY_PIN
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reti
short_sync:
; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz)
sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
jmp short_sync_end
; sync pin is high (sync is not occuring)
cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
; set timer in 2uS (reset timer counter)
ldi r27, high(TIMER_DELAY_2US)
ldi r26, low(TIMER_DELAY_2US)
sts TCNT1H,r27
sts TCNT1L,r26
; clear BUSY pin to indicate the mc is again responsive from now on
cbi PORTD, BUSY_PIN
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reti
short_sync_end:
; sync pin is low (sync is occuring)
sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
; set timer in 30uS:
ldi r27, high(TIMER_DELAY_30US)
ldi r26, low(TIMER_DELAY_30US)
sts TCNT1H,r27
sts TCNT1L,r26
; clear BUSY pin to indicate the mc is again responsive from now on
cbi PORTD, BUSY_PIN
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reti
empty_line:
; line sync: 4uS low (96 cycles @ 24Mhz), 60uS high (1440 cycles @ 24Mhz)
sbis PORTC, SYNC_PIN ; if sync is high (sync is not occuring) skip next line
jmp empty_line_end
; sync pin is high (sync is not occuring)
cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
; set timer in 2uS (reset timer counter)
ldi r27, high(TIMER_DELAY_4US)
ldi r26, low(TIMER_DELAY_4US)
sts TCNT1H,r27
sts TCNT1L,r26
; clear BUSY pin to indicate the mc is again responsive from now on
cbi PORTD, BUSY_PIN
reti
empty_line_end:
; sync pin is low (sync is occuring)
sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
; set timer in 30uS:
ldi r27, high(TIMER_DELAY_60US)
ldi r26, low(TIMER_DELAY_60US)
sts TCNT1H,r27
sts TCNT1L,r26
; clear BUSY pin to indicate the mc is again responsive from now on
cbi PORTD, BUSY_PIN
reti
draw_picture:
; save X register
push XH
push XL
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; set X register to framebuffer start
ldi r27, high(FRAMEBUFFER)
ldi r26, low(FRAMEBUFFER)
; start 304 picture lines
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ldi LINE_COUNTER, 256 ; line counter
h_picture_loop:
; **** start line sync: 4uS, 96 cycles @ 24Mhz
; video pin goes low before sync
clr VG_HIGH_ACCUM ; 1 cycle
out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle
cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
ldi VG_HIGH_ACCUM, 31 ; 1 cycle
l_sync_pulse_loop: ; requires 3 cpu cycles
dec VG_HIGH_ACCUM ; 1 cycle
brne l_sync_pulse_loop ; 2 cycle if true, 1 if false
sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
; **** end line sync
; **** start line back porch: 8uS, 192 cycles @ 24Mhz
; leave time at the end for line setup and draw_line call
ldi VG_HIGH_ACCUM, BACK_PORCH_DELAY/3 ; 1 cycle
l_sync_back_porch_loop:
dec VG_HIGH_ACCUM ; 1 cycle
brne l_sync_back_porch_loop ; 2 cycle if true, 1 if false
; **** end back porch
call draw_line ; 3 cycles (+ 3 to come back to on_line_drawn)
dec LINE_COUNTER ; decrement line countr ; 1 cycle
brne h_picture_loop ; if not 0, repeat h_picture_loop ; 2 cycle if true, 1 if false
; end picture lines
; restore X register
pop XL
pop XH
; video pin goes low before sync
clr VG_HIGH_ACCUM ; 1 cycle
out VIDEO_PORT_OUT, VG_HIGH_ACCUM ; 1 cycle
; immediately start first end-screen short sync:
inc STATUS
jmp short_sync
; reti is in short_sync
; end draw_picture
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draw_line:
; NO loops, as this is time-strict
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; 46 chunks of 8 pixels
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; chunk 1
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 2
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 3
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 4
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 5
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 6
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 7
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 8
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 9
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 10
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 11
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 12
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 13
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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; chunk 14
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
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nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 15
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 16
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 17
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 18
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 19
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 20
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 21
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 22
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 23
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 24
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 25
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 26
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 27
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 28
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 29
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 30
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 31
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 32
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 33
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 34
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 35
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 36
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 37
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 38
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 39
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 40
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 41
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 42
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 43
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 44
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 45
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
; chunk 46
ld A, X+ ; load pixel ; 2 cycles
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
nop ; 1 cycle
lsr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-01-19 08:36:01 +01:00
2021-02-14 18:29:24 +01:00
; blank right margin
2021-02-12 18:48:42 +01:00
clr A ; 1 cycle
out VIDEO_PORT_OUT, A ; 1 cycle
2021-02-14 18:29:24 +01:00
ldi VG_HIGH_ACCUM, 28 ; 1 cycle
2021-02-12 18:48:42 +01:00
eol_porch_loop: ; requires 3 cpu cycles
dec VG_HIGH_ACCUM ; 1 cycle
brne eol_porch_loop ; 2 if jumps, 1 if continues
2021-01-19 08:36:01 +01:00
ret