penguin86/pato-z80-home-computer
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Loses sync when loading from memory

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Daniele Verducci su MatissePenguin 2021-01-06 00:19:15 +01:00
parent 09785e1317
commit 06779c5442
1 changed files with 79 additions and 37 deletions
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116
pat80-io-devices/composite-pal-adapter/software/avr-assembly/main.asm
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@ -4,9 +4,12 @@
.include "atmega1284definition.asm" .include "atmega1284definition.asm"
; define constant ; define constant
.equ SYNC_PIN = PD7 ; Sync pin is on Port D 7 (pin 21) .equ SYNC_PIN = PC0 ; Sync pin (pin 22)
.equ VIDEO_PIN = PD6 ; Video pin is on Port D 6 (pin 20) .equ VIDEO_PIN = PD7 ; Video pin (pin 21)
.equ DEBUG_PIN = PD5 ; Video pin is on Port D 5 (pin 19) .equ DEBUG_PIN = PC1 ; DEBUG: Single vertical sync pulse to trigger oscilloscope (pin 23)
; memory
.equ FRAMEBUFFER = 0x100
; start vector ; start vector
.org 0x0000 .org 0x0000
@ -14,11 +17,39 @@
; main program ; main program
main: main:
sbi DDRD, SYNC_PIN ; set pin as output sbi DDRC, SYNC_PIN ; set pin as output
sbi DDRD, VIDEO_PIN ; set pin as output sbi DDRC, DEBUG_PIN ; set pin as output
sbi DDRD, DEBUG_PIN ; set pin as output ldi r16, 0xFF
out DDRD, r16 ; set port as output
; Load ram addr into register X
ldi r16,0x00
mov r0,r16
ldi r16,0x01
mov r1,r16
mov XL,r0
mov XH,r1
; DEBUG: loads some static data in ram
ldi r18, 255
fill_mem_loop1:
st X+, r18
dec r18
brne fill_mem_loop1
; END DEBUG
v_refresh_loop: v_refresh_loop:
; reset memory position counter
;ldi XL, 0x00
;ldi XH, 0x01
ldi r16,0x00
mov r0,r16
ldi r16,0x01
mov r1,r16
mov XL,r0
mov XH,r1
; start 5 long sync pulses ; start 5 long sync pulses
call long_sync call long_sync
call long_sync call long_sync
@ -41,31 +72,42 @@ v_refresh_loop:
ldi r17, 152 ; line counter ldi r17, 152 ; line counter
h_picture_loop: h_picture_loop:
call line_sync call line_sync
; start image: 52uS, 1247 cycles @ 24Mhz ; start line pixels: 52uS, 1247 cycles @ 24Mhz
; 3 bande da 416 cicli ldi r18, 52 ; 1 cycle
l_sync_video_loop: ; 24 cycles
; Load a byte from memory into PORTD register and increment the counter.
; This also displays byte's MSB pixel "for free", as the video pin is PD7
; (last bit of PORTD).
;ld r19, X+ ; 2 cycles
ld r19, X ; 1 cycle
nop
ldi r18, 59 ; 1 cycle out PORTD, r19 ; 1 cycle
l_sync_video_loop1: ; Shift the byte to the left to show another bit (do it 7 times)
sbi PORTD, VIDEO_PIN ; video goes high ; 2 cycle lsl r19 ; 1 cycle
dec r18 ; 1 cycle out PORTD, r19
cbi PORTD, VIDEO_PIN ; video goes low ; 2 cycle nop
brne l_sync_video_loop1 ; 2 cycle if true, 1 if false lsl r19 ; 1 cycle
out PORTD, r19
ldi r18, 137 ; 1 cycle nop
l_sync_video_loop2: lsl r19 ; 1 cycle
dec r18 ; 1 cycle out PORTD, r19
brne l_sync_video_loop2 ; 2 cycle if true, 1 if false nop
lsl r19 ; 1 cycle
sbi PORTD, VIDEO_PIN ; video goes high out PORTD, r19
nop
ldi r18, 138 ; 1 cycle lsl r19 ; 1 cycle
l_sync_video_loop3: out PORTD, r19
dec r18 ; 1 cycle nop
brne l_sync_video_loop3 ; 2 cycle if true, 1 if false lsl r19 ; 1 cycle
cbi PORTD, VIDEO_PIN ; video goes low out PORTD, r19
nop ; 1 cycle
; end image dec r18 ; 1 cycle
brne l_sync_video_loop ; 2 cycles if jumps (1 if continues)
; end line pixels
cbi PORTD, VIDEO_PIN ; video pin goes low before sync
dec r17 ; decrement line counter dec r17 ; decrement line counter
brne h_picture_loop ; if not 0, repeat h_picture_loop brne h_picture_loop ; if not 0, repeat h_picture_loop
@ -83,8 +125,8 @@ v_refresh_loop:
; end 6 short sync pulses ; end 6 short sync pulses
; debug ; debug
sbi PORTD, DEBUG_PIN ; high sbi PORTC, DEBUG_PIN ; high
cbi PORTD, DEBUG_PIN ; low cbi PORTC, DEBUG_PIN ; low
; debug ; debug
jmp v_refresh_loop jmp v_refresh_loop
@ -92,7 +134,7 @@ v_refresh_loop:
long_sync: long_sync:
; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz) ; long sync: 30uS low (719 cycles @ 24Mhz), 2uS high (48 cycles @ 24Mhz)
cbi PORTD, SYNC_PIN ; sync goes low (0v) ; 2 cycle cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
ldi r18, 120 ; 1 cycle ldi r18, 120 ; 1 cycle
long_sync_low_loop: ; requires 6 cpu cycles long_sync_low_loop: ; requires 6 cpu cycles
@ -102,7 +144,7 @@ long_sync:
dec r18 ; 1 cycle dec r18 ; 1 cycle
brne long_sync_low_loop ; 2 cycle if true, 1 if false brne long_sync_low_loop ; 2 cycle if true, 1 if false
sbi PORTD, SYNC_PIN ; sync goes high (0.3v) sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
ldi r18, 15 ; 1 cycle ldi r18, 15 ; 1 cycle
long_sync_high_loop: ; requires 3 cpu cycles long_sync_high_loop: ; requires 3 cpu cycles
@ -113,14 +155,14 @@ long_sync:
short_sync: short_sync:
; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz) ; short sync: 2uS low (48 cycles @ 24Mhz), 30uS high (720 cycles @ 24Mhz)
cbi PORTD, SYNC_PIN ; sync goes low (0v) ; 2 cycle cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
ldi r18, 15 ; 1 cycle ldi r18, 15 ; 1 cycle
short_sync_low_loop: ; requires 3 cpu cycles short_sync_low_loop: ; requires 3 cpu cycles
dec r18 ; 1 cycle dec r18 ; 1 cycle
brne short_sync_low_loop ; 2 cycle if true, 1 if false brne short_sync_low_loop ; 2 cycle if true, 1 if false
sbi PORTD, SYNC_PIN ; sync goes high (0.3v) sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
ldi r18, 120 ; 1 cycle ldi r18, 120 ; 1 cycle
short_sync_high_loop: ; requires 6 cpu cycles short_sync_high_loop: ; requires 6 cpu cycles
@ -135,12 +177,12 @@ short_sync:
line_sync: line_sync:
; line sync & front porch ; line sync & front porch
; start line sync: 4uS, 96 cycles @ 24Mhz ; start line sync: 4uS, 96 cycles @ 24Mhz
cbi PORTD, SYNC_PIN ; sync goes low (0v) ; 2 cycle cbi PORTC, SYNC_PIN ; sync goes low (0v) ; 2 cycle
ldi r18, 32 ; 1 cycle ldi r18, 32 ; 1 cycle
l_sync_pulse_loop: ; requires 3 cpu cycles l_sync_pulse_loop: ; requires 3 cpu cycles
dec r18 ; 1 cycle dec r18 ; 1 cycle
brne l_sync_pulse_loop ; 2 cycle if true, 1 if false brne l_sync_pulse_loop ; 2 cycle if true, 1 if false
sbi PORTD, SYNC_PIN ; sync goes high (0.3v) sbi PORTC, SYNC_PIN ; sync goes high (0.3v)
; end line sync ; end line sync
; start back porch: 8uS, 192 cycles @ 24Mhz ; start back porch: 8uS, 192 cycles @ 24Mhz